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1. 发明授权

US06414347B1 Vertical MOSFET 失效
标题翻译：垂直MOSFET
公开(公告)号：US06414347B1
公开(公告)日：2002-07-02
申请号：US09790011
申请日：2001-02-09
申请人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
发明人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
IPC分类号： H01L2972
CPC分类号： H01L27/10864 , H01L21/2255 , H01L21/26586 , H01L27/10841 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.
摘要翻译：一种用于制造垂直MOSFET结构的改进方法，包括：一种形成半导体存储单元阵列结构的方法，包括：提供垂直MOSFET DRAM单元结构，其具有平坦化到覆盖硅上的沟槽顶部氧化物的顶表面的沉积栅极导体层基质; 在所述硅衬底的顶表面下方的所述栅极导体层中形成凹部; 以一定角度注入N型掺杂剂物质通过凹槽形成阵列P-阱中的掺杂凹坑; 将氧化物层沉积到所述凹部中并蚀刻所述氧化物层以在所述凹部的侧壁上形成间隔物; 将栅极导体材料沉积到所述凹部中并将所述栅极导体平坦化到所述沟槽顶部氧化物的所述顶表面。

2. 发明授权

US06440793B1 Vertical MOSFET 失效
公开(公告)号：US06440793B1
公开(公告)日：2002-08-27
申请号：US09757514
申请日：2001-01-10
申请人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
发明人： Ramachandra Divakaruni , Heon Lee , Jack A. Mandelman , Carl J. Radens , Jai-Hoon Sim
IPC分类号： H01L218242
CPC分类号： H01L27/10841 , H01L21/2255 , H01L21/26586 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

3. 发明授权

US06441422B1 Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well 失效
标题翻译：具有接触P阱的超可扩展混合DRAM单元的结构和方法
公开(公告)号：US06441422B1
公开(公告)日：2002-08-27
申请号：US09706482
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Jai-hoon Sim
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Jai-hoon Sim
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867
摘要： An ultra-scalable hybrid memory cell having a low junction leakage and a process of fabricating the same are provided. The ultra-scalable hybrid memory cell contains a conductive connection to the body region therefore avoiding isolation of the P-well due to cut-off by the buried strap outdiffusion region. The ultra-scalable hybrid memory cell avoids the above by using a shallower than normal isolation region that allows the P-well to remain connected to the body of the memory cell.
摘要翻译：提供具有低结漏电的超可扩展混合存储器单元及其制造工艺。超可扩展混合存储器单元包含与身体区域的导电连接，从而避免由于掩埋带外扩散区域而导致的P阱的隔离。超可扩展混合存储器单元通过使用允许P阱保持连接到存储器单元的主体的比普通隔离区更浅的方式来避免上述情况。

4. 发明申请

US20090176339A1 Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效
标题翻译：在单元中并联连接沟槽电容器的多端口存储器制造方法
公开(公告)号：US20090176339A1
公开(公告)日：2009-07-09
申请号：US12316748
申请日：2008-12-16
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译：提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。

5. 发明授权

US06455886B1 Structure and process for compact cell area in a stacked capacitor cell array 失效
标题翻译：叠层电容器阵列中紧凑单元面积的结构和工艺
公开(公告)号：US06455886B1
公开(公告)日：2002-09-24
申请号：US09636564
申请日：2000-08-10
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L29/66181
摘要： A method for forming, and a structure for a semiconductor device having vertically-oriented transistors connected to stacked capacitor cells, wherein a contact area for the capacitors enables a compact cell. A vertically-oriented transistor is formed in a trough in a substrate above a buried bit line. The gate conductor may be formed in the trough above the buried bit line, with source and drain diffusions spaced along a sidewall of the trough. Isolation regions are formed in the semiconductor substrate to isolate the transistors. Word lines are formed above the surface of the semiconductor substrate in a direction perpendicular to the direction of the buried bit lines. A capacitor contact is formed above the surface of the semiconductor substrate at a contact area of an active region between adjacent word lines. The active region is rhomboid in shape, enabling a low capacitor contact resistance, a small bit line and word line pitch, and consequently, a compact capacitor cell.
摘要翻译：一种用于形成的方法，以及具有连接到层叠电容器单元的垂直取向的晶体管的半导体器件的结构，其中电容器的接触面积使得能够实现紧凑的电池。垂直取向的晶体管形成在掩埋位线上方的衬底的槽中。栅极导体可以形成在掩埋位线上方的槽中，源极和漏极扩散沿着槽的侧壁间隔开。在半导体衬底中形成隔离区以隔离晶体管。在与掩埋位线的方向垂直的方向上在半导体衬底的表面上形成字线。在相邻字线之间的有源区域的接触区域处，在半导体衬底的表面上方形成电容器触点。有源区域是菱形形状，能够实现低电容器接触电阻，小位线和字线间距，从而实现紧凑的电容器单元。

6. 发明授权

US06440872B1 Method for hybrid DRAM cell utilizing confined strap isolation 失效
标题翻译：混合DRAM单元利用限制带隔离的方法
公开(公告)号：US06440872B1
公开(公告)日：2002-08-27
申请号：US09706468
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Stephan Kudelka
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Stephan Kudelka
IPC分类号： H01L2100
CPC分类号： H01L27/10867 , H01L27/10876
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.
摘要翻译：形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

7. 发明授权

US06261894B1 Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays 有权
标题翻译：在EDRAM阵列中形成双功能高性能支持MOSFET的方法
公开(公告)号：US06261894B1
公开(公告)日：2001-07-17
申请号：US09706492
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L218234
CPC分类号： H01L27/10864 , H01L27/10894 , H01L27/10897
摘要： Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in the forming memory structure, decouple the support and arraying processing steps, provide salicided gates, source/drain regions and bitlines, and provide, in some instances, local interconnects at no additional processing costs. Dual workfunction high-performance support MOSFETs/ EDRAM arrays having a gate conductor guard ring and/or local interconnections are also provided.
摘要翻译：提供双功能功能高性能支持金属氧化物半导体场效应晶体管（MOSFET）/嵌入式动态随机存取（EDRAM）阵列的方法。这里描述的方法减少了在形成存储器结构中使用的深UV掩模的数量，解耦支持和排列处理步骤，提供盐化栅极，源极/漏极区域和位线，并且在一些情况下提供局部互连，加工成本。还提供了双功能功能的高性能支持具有栅极导体保护环和/或局部互连的MOSFET / EDRAM阵列。

8. 发明授权

US07785959B2 Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效
标题翻译：在单元中并联连接沟槽电容器的多端口存储器制造方法
公开(公告)号：US07785959B2
公开(公告)日：2010-08-31
申请号：US12316748
申请日：2008-12-16
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译：提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。

9. 发明授权

US06759702B2 Memory cell with vertical transistor and trench capacitor with reduced burried strap 有权
标题翻译：具有垂直晶体管和沟槽电容器的存储单元，具有减少的挂带
公开(公告)号：US06759702B2
公开(公告)日：2004-07-06
申请号：US10261559
申请日：2002-09-30
申请人： Carl J. Radens , Ramachandra Divakaruni , Jack A. Mandelman
发明人： Carl J. Radens , Ramachandra Divakaruni , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/66181 , H01L29/945
摘要： A memory cell structure including a semiconductor substrate, a deep (e.g., longitudinal) trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom, a buried strap along a sidewall of the deep trench, a storage capacitor at the bottom of the deep trench, a vertical transistor extending down the sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench, a collar oxide extending down another sidewall of the deep trench opposite the capacitor, shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends, a gate conductor extending within the deep trench, a wordline extending over the deep trench and connected to the gate conductor, and a bitline extending above the surface plane of the substrate having a contact to the diffusion between the shallow trench isolation regions. The deep trench has a perimeter in a direction normal to its depth, and the buried strap extends a distance along the perimeter, the distance being only within a range of 5% to 20% of the entire linear distance along the perimeter, and being less than one lithographic feature size. Preferably, the strap in a direction along the perimeter is curved and is disposed along only one corner of the perimeter. The structure is particularly useful for a sub-8F2 cell.
摘要翻译：一种存储单元结构，包括半导体衬底，半导体衬底中的深（例如，纵向）沟槽，深沟槽具有多个侧壁和底部，沿着深沟槽的侧壁的掩埋带，存储电容器深沟槽的底部，垂直晶体管，沿着存储电容器上方的深沟槽的侧壁向下延伸，晶体管具有在衬底的与深沟槽相邻的平面中延伸的扩散，从深沟槽的另一个侧壁延伸的环状氧化物与电容器相对的浅沟槽隔离区域沿垂直于垂直晶体管延伸的侧壁横向的衬底表面延伸，在深沟槽内延伸的栅极导体，延伸在深沟槽上并与栅极导体连接的字线以及在衬底的表面平面上方延伸的位线，该位线与浅沟槽iso之间的扩散接触国际地区。深沟槽在垂直于其深度的方向上具有周长，并且掩埋带沿着周边延伸一段距离，该距离仅在沿着周边的整个线性距离的5％至20％的范围内，并且更小比一个光刻特征尺寸。优选地，沿着周边的方向上的带子是弯曲的并且沿着周边的一个角部设置。该结构对于亚8F 2细胞特别有用。

10. 发明授权

US06339241B1 Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch 有权
公开(公告)号：US06339241B1
公开(公告)日：2002-01-15
申请号：US09602426
申请日：2000-06-23
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens , Ulrike Gruening
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.

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