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1. 发明申请

US20100070894A1 FEDERATED CALENDAR ENTRY PRESENCE INDICATOR 审中-公开
标题翻译：联合日历录入指示
公开(公告)号：US20100070894A1
公开(公告)日：2010-03-18
申请号：US12211401
申请日：2008-09-16
申请人： Ram Krishnamurthy , John M. Lance , Frank A. Pavelski
发明人： Ram Krishnamurthy , John M. Lance , Frank A. Pavelski
IPC分类号： G06F3/048
CPC分类号： G06F3/0481
摘要： A method for indicating the presence of federated calendar entries in a currently viewed time period of a calendar and/or scheduling application, includes: receiving a user's selection for a date range in a calendar and/or scheduling application; determining whether there are one or more federated calendars associated with the user's calendar and/or scheduling application; wherein in the event there are one or more federated calendars associated with the user's calendar and/or scheduling application: determining whether there are one or more events from the one or more federated calendars in the selected date range; and wherein in the event there are federated calendar events in the selected date range: generating a calendar and/or scheduling page with one or more indicators for federated calendars with events in the selected date range.
摘要翻译：一种用于指示在日历和/或调度应用的当前观看时间段中存在联合日历条目的方法，包括：在日历和/或调度应用中接收用户对日期范围的选择; 确定是否存在与用户的日历和/或调度应用相关联的一个或多个联合日历; 其中在所述事件中存在与所述用户日历和/或调度应用程序相关联的一个或多个联合日历：确定在所选择的日期范围内是否存在来自所述一个或多个联合日历的一个或多个事件; 并且其中在所述选择的日期范围内存在联合日历事件的情况下：在具有所选日期范围内的事件的联合日历中生成具有一个或多个指示符的日历和/或调度页面。

2. 发明授权

US08407075B2 Merging calendar entries 失效
标题翻译：合并日历条目
公开(公告)号：US08407075B2
公开(公告)日：2013-03-26
申请号：US12823417
申请日：2010-06-25
申请人： John M. Lance , David B. Cohen , Bruce A. Kahn , Gregory R. Klouda , Ram Krishnamurthy , Deborah E. Maurer , Frank A. Pavelski , Michelle Stoner
发明人： John M. Lance , David B. Cohen , Bruce A. Kahn , Gregory R. Klouda , Ram Krishnamurthy , Deborah E. Maurer , Frank A. Pavelski , Michelle Stoner
IPC分类号： G06Q10/00
CPC分类号： G06F3/0482 , G06Q10/109
摘要： A method, operable on a processing device, for merging calendar entries may include receiving a plurality of calendar entries each associated with entry identification data. The method may also include comparing by the processing device at least a portion of the entry identification data associated with each of the calendar entries. The method may additionally include merging, by the processing device, the calendar entries based at least in part on comparing of at least the portion of the entry identification data associated with each of the at least two calendar entries. The method may further include comparing at least one time attribute associated with each of the calendar entries and comparing at least one textual attribute associated with each of the calendar entries and basing merging the calendar entries additionally on comparing the time attributes and the textual attributes.
摘要翻译：可在处理装置上操作用于合并日历条目的方法可以包括接收与条目标识数据相关联的多个日历条目。该方法还可以包括通过处理设备比较与每个日历条目相关联的条目标识数据的至少一部分。该方法可以另外包括至少部分地基于与至少两个日历条目中的每一个相关联的条目标识数据的至少一部分的比较来由处理设备合并日历条目。该方法还可以包括比较与每个日历条目相关联的至少一个时间属性，并比较与每个日历条目相关联的至少一个文本属性，并且在比较时间属性和文本属性的基础上逐步合并日历条目。

3. 发明申请

US20190057300A1 WEIGHT PREFETCH FOR IN-MEMORY NEURAL NETWORK EXECUTION 审中-公开
公开(公告)号：US20190057300A1
公开(公告)日：2019-02-21
申请号：US16160466
申请日：2018-10-15
申请人： Amrita Mathuriya , Sasikanth Manipatruni , Victor Lee , Huseyin Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , IAN YOUNG , Abhishek Sharma
发明人： Amrita Mathuriya , Sasikanth Manipatruni , Victor Lee , Huseyin Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , IAN YOUNG , Abhishek Sharma
IPC分类号： G06N3/04 , G06F3/06 , G06F12/0875
摘要： The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nth layer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)st layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)st layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.

4. 发明申请

US20190057036A1 PROGRAMMABLE INTERFACE TO IN-MEMORY CACHE PROCESSOR 审中-公开
公开(公告)号：US20190057036A1
公开(公告)日：2019-02-21
申请号：US16160270
申请日：2018-10-15
申请人： Amrita Mathuriya , Sasikanth Manipatruni , Victor Lee , Huseyin Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , IAN YOUNG , Abhishek Sharma
发明人： Amrita Mathuriya , Sasikanth Manipatruni , Victor Lee , Huseyin Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , IAN YOUNG , Abhishek Sharma
IPC分类号： G06F12/0875 , G06N3/063 , G06N3/04 , G06F3/06
摘要： The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

5. 发明申请

US20150086007A1 COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT 有权
标题翻译：紧凑型低功耗高级加密标准电路
公开(公告)号：US20150086007A1
公开(公告)日：2015-03-26
申请号：US14035508
申请日：2013-09-24
申请人： Sanu MATHEW , Vikram Suresh , Sudhir Satpathy , Mark Anders , Himanshu Kaul , Ram Krishnamurthy
发明人： Sanu MATHEW , Vikram Suresh , Sudhir Satpathy , Mark Anders , Himanshu Kaul , Ram Krishnamurthy
IPC分类号： H04L9/30
CPC分类号： H04L9/0631 , H04L2209/24
摘要： Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.
摘要翻译：公开了一种用于紧凑型低功率高级加密标准电路的发明的实施例。在一个实施例中，装置包括具有替换盒和累加器的加密单元。替代方案是对每个时钟周期的一个字节执行替换操作。累加器将累积四个字节，并在四个时钟周期内执行混合列操作。加密单元使用最小区域的最优伽罗瓦域多项式运算来实现。

6. 发明申请

US20140201540A1 SECURE KEY STORAGE USING PHYSICALLY UNCLONABLE FUNCTIONS 有权
标题翻译：使用物理不可靠函数确保关键存储
公开(公告)号：US20140201540A1
公开(公告)日：2014-07-17
申请号：US13996544
申请日：2011-12-29
申请人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
发明人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
IPC分类号： H04L9/08
CPC分类号： H04L9/0891 , G09C1/00 , H04L9/0822 , H04L9/0861 , H04L9/0866 , H04L9/0894 , H04L2209/12
摘要： Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.
摘要翻译：本文公开的一些实施例提供了用于向集成电路/处理器供应密钥的技术和布置处理器可以包括物理上不可克隆的功能组件，其可以至少基于处理器的至少一个物理特性来生成唯一的硬件密钥。硬件密钥可用于加密诸如秘密密钥的密钥。加密密钥可以存储在处理器的存储器中。可以验证加密的密钥。可以通过通信地隔离处理器的至少一个组件来保护密钥的完整性。

7. 发明申请

US20140013082A1 RECONFIGURABLE DEVICE FOR REPOSITIONING DATA WITHIN A DATA WORD 审中-公开
标题翻译：用于在数据字中记录数据的可重新配置的设备
公开(公告)号：US20140013082A1
公开(公告)日：2014-01-09
申请号：US13976923
申请日：2011-12-30
申请人： Amit Agarwal , Steven Hsu , Ram Krishnamurthy
发明人： Amit Agarwal , Steven Hsu , Ram Krishnamurthy
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30036
摘要： Disclosed is a system and device and related methods for data manipulation, especially for SIMD operations such as permute, shift, and rotate. An apparatus includes a permute section that repositions data on sub-word boundaries and a shift section that repositions the data distances smaller than the sub-word width. The sub-word width is configurable and selectable, and the permute section and shift section may operate on different boundary widths. In a first stage, the permute section repositions the data at the nearest sub-word boundary and, in a second stage, the shift section repositions the data to its final desired position. The shift section includes multi-stages set in a logarithmic cascade relationship. Additionally, each shifter within each of the multi-stages is highly connected, allowing fast and precise data movements.
摘要翻译：公开了一种用于数据操作的系统和设备及相关方法，特别是用于SIMD操作，例如置换，移位和旋转。一种装置包括：重新定位子字边界上的数据的置换部分和重新定位小于子字宽度的数据距离的移位部分。子字宽度是可配置和可选择的，并且置换部分和移位部分可以在不同的边界宽度上操作。在第一阶段中，置换部分将数据重新定位在最近的子字边界处，并且在第二阶段中，移位部分将数据重新定位到其最终期望的位置。移位部分包括以对数级联关系设置的多级。另外，每个多级中的每个移位器是高度连接的，允许快速和精确的数据移动。

8. 发明授权

US08284766B2 Multi-core processor and method of communicating across a die 有权
标题翻译：多核处理器和跨模块通信的方法
公开(公告)号：US08284766B2
公开(公告)日：2012-10-09
申请号：US11966327
申请日：2007-12-28
申请人： Mark Anders , Himanshu Kaul , Ram Krishnamurthy , Shekhar Borkar
发明人： Mark Anders , Himanshu Kaul , Ram Krishnamurthy , Shekhar Borkar
IPC分类号： H04L12/66
CPC分类号： G06F15/17375 , G06F15/7825 , Y02D10/12 , Y02D10/13
摘要： A multi-core die is provided that allows packets to be communicated across the die using resources of a packet switched network and a circuit switched network.
摘要翻译：提供了一种多核管芯，其允许使用分组交换网络和电路交换网络的资源在管芯上传送分组。

9. 发明授权

US07900160B2 System and method for illustrating a menu of insights associated with visualizations 失效
标题翻译：用于说明与可视化相关联的见解菜单的系统和方法
公开(公告)号：US07900160B2
公开(公告)日：2011-03-01
申请号：US10745500
申请日：2003-12-29
申请人： Paul B. Moody , Cynthia L. Ice , Douglas W. Conmy , Mary Elizabeth Raven , Jodi L. Coppinger , Francis D. Bermingham , Ram Krishnamurthy
发明人： Paul B. Moody , Cynthia L. Ice , Douglas W. Conmy , Mary Elizabeth Raven , Jodi L. Coppinger , Francis D. Bermingham , Ram Krishnamurthy
IPC分类号： G06F3/048
CPC分类号： G06F3/0481
摘要： A system and method are provided for generating one or more menus having options that display insights from visualizations. The options presented in the menus enable users to determine relationships between elements of the visualization. The relationships may be displayed textually to enable user to navigate the menus using a keyboard, a text-to-voice converter, and/or pointers.
摘要翻译：提供了一种系统和方法，用于生成具有从可视化显示洞察力的选项的一个或多个菜单。菜单中显示的选项使用户能够确定可视化元素的关系。可以以文字方式显示关系，以使用户能够使用键盘，文本到语音转换器和/或指针来导航菜单。

10. 发明授权

US07860240B2 Native composite-field AES encryption/decryption accelerator circuit 有权
标题翻译：本地复合场AES加密/解密加速器电路
公开(公告)号：US07860240B2
公开(公告)日：2010-12-28
申请号：US11771723
申请日：2007-06-29
申请人： Sanu Mathew , Farhana Sheikh , Ram Krishnamurthy
发明人： Sanu Mathew , Farhana Sheikh , Ram Krishnamurthy
IPC分类号： H04K1/10
CPC分类号： H04L9/0631 , H04L2209/12
摘要： A system comprises reception of input data of a Galois field GF(2k), mapping of the input data to a composite Galois field GF(2nm), where k=nm, inputting of the mapped input data to an Advanced Encryption Standard round function, performance of two or more iterations of the Advanced Encryption Standard round function in the composite Galois field GF(2nm), reception of output data of a last of the two or more iterations of the Advanced Encryption Standard round function, and mapping of the output data to the Galois field GF(2k).
摘要翻译：一种系统包括接收伽罗瓦域GF（2k）的输入数据，将输入数据映射到复合伽罗瓦域GF（2nm），其中k = nm，将映射的输入数据输入到高级加密标准循环函数，在复合伽罗瓦域GF（2nm）中执行高级加密标准循环函数的两次或更多次迭代的执行，对高级加密标准循环函数的两次或更多次迭代的最后一次的输出数据的接收以及输出数据的映射到Galois字段GF（2k）。

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