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1. 发明授权

US09544133B2 On-the-fly key generation for encryption and decryption 有权
标题翻译：用于加密和解密的即时密钥生成
公开(公告)号：US09544133B2
公开(公告)日：2017-01-10
申请号：US12647459
申请日：2009-12-26
申请人： Sanu K. Mathew , Farhana Sheikh , Ram K. Krishnamurthy , Michael E. Kounavis , Shay Gueron
发明人： Sanu K. Mathew , Farhana Sheikh , Ram K. Krishnamurthy , Michael E. Kounavis , Shay Gueron
IPC分类号： H04L9/00 , H04L9/06 , H04L9/30
CPC分类号： H04L9/0631 , H04L9/3073 , H04L2209/24
摘要： Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.
摘要翻译：描述了为Galois Field（也称为有限场）加密和/或解密提供实时密钥计算的方法和装置。在一个实施例中，逻辑在第二周期中基于在紧接在第二周期之前的第一周期中生成的先前密码密钥来生成密码密钥。还描述了其它实施例。

2. 发明申请

US20150178143A1 USING DARK BITS TO REDUCE PHYSICAL UNCLONABLE FUNCTION (PUF) ERROR RATE WITHOUT STORING DARK BITS LOCATION 有权
标题翻译：使用深色位置减少物理不可靠功能（PUF）错误率，而不会存储明显的位置
公开(公告)号：US20150178143A1
公开(公告)日：2015-06-25
申请号：US14140243
申请日：2013-12-24
申请人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
发明人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F7/00 , G06F7/588 , G06F11/0745 , G11C7/24 , H04L9/3278 , H04L9/34
摘要： Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.
摘要翻译：描述了用于物理不可克隆功能（PUF）组件的暗位掩蔽技术。计算系统包括处理器核心和耦合到处理器核心的安全密钥管理器组件。安全密钥管理器包括PUF组件和耦合到PUF组件的暗位屏蔽电路。暗位掩蔽电路是在暗位窗口期间多次测量PUF分量的PUF值，以检测PUF分量的PUF值是否为暗位。暗位表示PUF组件的PUF值在暗位窗口期间不稳定。当PUF值不是暗位时，暗位屏蔽电路将输出PUF值作为PUF分量的输出PUF位，并且当PUF分量的PUF值为黑暗的一点

3. 发明申请

US20140201540A1 SECURE KEY STORAGE USING PHYSICALLY UNCLONABLE FUNCTIONS 有权
标题翻译：使用物理不可靠函数确保关键存储
公开(公告)号：US20140201540A1
公开(公告)日：2014-07-17
申请号：US13996544
申请日：2011-12-29
申请人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
发明人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
IPC分类号： H04L9/08
CPC分类号： H04L9/0891 , G09C1/00 , H04L9/0822 , H04L9/0861 , H04L9/0866 , H04L9/0894 , H04L2209/12
摘要： Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.
摘要翻译：本文公开的一些实施例提供了用于向集成电路/处理器供应密钥的技术和布置处理器可以包括物理上不可克隆的功能组件，其可以至少基于处理器的至少一个物理特性来生成唯一的硬件密钥。硬件密钥可用于加密诸如秘密密钥的密钥。加密密钥可以存储在处理器的存储器中。可以验证加密的密钥。可以通过通信地隔离处理器的至少一个组件来保护密钥的完整性。

4. 发明申请

US20110158403A1 ON-THE-FLY KEY GENERATION FOR ENCRYPTION AND DECRYPTION 有权
标题翻译：用于加密和分解的关键生成器
公开(公告)号：US20110158403A1
公开(公告)日：2011-06-30
申请号：US12647459
申请日：2009-12-26
申请人： Sanu K. Mathew , Farhana Sheikh , Ram K. Krishnamurthy , Michael E. Kounavis , Shay Gueron
发明人： Sanu K. Mathew , Farhana Sheikh , Ram K. Krishnamurthy , Michael E. Kounavis , Shay Gueron
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , H04L9/3073 , H04L2209/24
摘要： Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.
摘要翻译：描述了为Galois Field（也称为有限场）加密和/或解密提供实时密钥计算的方法和装置。在一个实施例中，逻辑在第二周期中基于在紧接在第二周期之前的第一周期中生成的先前密码密钥来生成密码密钥。还描述了其它实施例。

5. 发明申请

US20170187388A1 Hardware apparatuses and methods for data decompression 审中-公开
公开(公告)号：US20170187388A1
公开(公告)日：2017-06-29
申请号：US14757854
申请日：2015-12-26
申请人： Sudhir K. Satpathy , James D. Guilford , Sanu K. Mathew , Vinodh Gopal , Vikram B. Suresh
发明人： Sudhir K. Satpathy , James D. Guilford , Sanu K. Mathew , Vinodh Gopal , Vikram B. Suresh
IPC分类号： H03M7/30 , G06F9/30
CPC分类号： H03M7/3082 , G06F9/3877 , G06F9/46 , H03M7/4037 , H03M7/6005 , H03M7/6011 , H03M7/6017 , H03M7/6052
摘要： Methods and apparatuses relating to data decompression are described. In one embodiment, a hardware processor includes a core to execute a thread and offload a decompression thread for an encoded, compressed data stream comprising a literal code, a length code, and a distance code, and a hardware decompression accelerator to execute the decompression thread to selectively provide the encoded, compressed data stream to a first circuit to serially decode the literal code to a literal symbol, serially decode the length code to a length symbol, and serially decode the distance code to a distance symbol, and selectively provide the encoded, compressed data stream to a second circuit to look up the literal symbol for the literal code from a table, look up the length symbol for the length code from the table, and look up the distance symbol for the distance code from the table.

6. 发明申请

US20160188533A1 Systems, Apparatuses, and Methods for K Nearest Neighbor Search 有权
标题翻译： K最近邻搜索的系统，设备和方法
公开(公告)号：US20160188533A1
公开(公告)日：2016-06-30
申请号：US14582607
申请日：2014-12-24
申请人： Himanshu KAUL , Mark A. ANDERS , Sanu K. MATHEW
发明人： Himanshu KAUL , Mark A. ANDERS , Sanu K. MATHEW
IPC分类号： G06F15/80
CPC分类号： G06F15/8092 , G06F7/00 , G06F17/3033
摘要： Systems, apparatuses, and methods for k-nearest neighbor (KNN) searches are described. In particular, embodiments of a KNN accelerator and its uses are described. In some embodiments, the KNN accelerator includes a plurality of vector partial distance computation circuits each to calculate a partial sum, a minimum sort network to sort partial sums from the plurality of vector partial distance computation circuits to find k nearest neighbor matches and a global control circuit to control aspects of operations of the plurality of vector partial distance computation circuits.
摘要翻译：描述了k-最近邻（KNN）搜索的系统，装置和方法。特别地，描述了KNN加速器的实施例及其用途。在一些实施例中，KNN加速器包括多个矢量部分距离计算电路，每个矢量部分距离计算电路各自计算部分和，最小分类网络对来自多个矢量部分距离计算电路的部分和进行排序以找到最近邻匹配和全局控制电路以控制多个矢量部分距离计算电路的操作的方面。

7. 发明授权

US09262256B2 Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location 有权
标题翻译：使用暗位来减少物理不可克隆功能（PUF）错误率，而不存储暗位置
公开(公告)号：US09262256B2
公开(公告)日：2016-02-16
申请号：US14140243
申请日：2013-12-24
申请人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
发明人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
IPC分类号： G06F21/00 , H04L29/06 , G06F11/07 , G11C7/24 , G11C7/00 , G06F7/58 , H04L9/34
CPC分类号： G06F11/0793 , G06F7/00 , G06F7/588 , G06F11/0745 , G11C7/24 , H04L9/3278 , H04L9/34
摘要： Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.
摘要翻译：描述了用于物理不可克隆功能（PUF）组件的暗位掩蔽技术。计算系统包括处理器核心和耦合到处理器核心的安全密钥管理器组件。安全密钥管理器包括PUF组件和耦合到PUF组件的暗位屏蔽电路。暗位掩蔽电路是在暗位窗口期间多次测量PUF分量的PUF值，以检测PUF分量的PUF值是否为暗位。暗位表示PUF组件的PUF值在暗位窗口期间不稳定。当PUF值不是暗位时，暗位屏蔽电路将输出PUF值作为PUF分量的输出PUF位，并且当PUF分量的PUF值为黑暗的一点

8. 发明申请

US20150381202A1 HYBRID CAM ASSISTED DEFLATE DECOMPRESSION ACCELERATOR 有权
标题翻译：混合辅助辅助解码加速器
公开(公告)号：US20150381202A1
公开(公告)日：2015-12-31
申请号：US14317698
申请日：2014-06-27
申请人： SUDHIR K. SATPATHY , SANU K. MATHEW , VINODH GOPAL , RAM K. KRISHNAMURTHY
发明人： SUDHIR K. SATPATHY , SANU K. MATHEW , VINODH GOPAL , RAM K. KRISHNAMURTHY
IPC分类号： H03M7/42 , G06F12/06
CPC分类号： G06F12/0646 , G06F2212/1021 , G06F2212/401 , G11C15/00 , G11C15/04 , H03M7/3059 , H03M7/3084 , H03M7/3086 , H03M7/40
摘要： Disclosed is an integrated circuit including a memory device including a first portion and a second portion. The first portion is a first type of content addressable memory (CAM) with a first set of cells and the second portion is a second type of CAM with a second set of cells. The first set of cells is smaller than the second set of cells. The integrated circuit further includes a decompression accelerator coupled to the memory device, the decompression accelerator to generate a plurality of length codes. Each of the plurality of length codes include at least one bit. The plurality of length codes are generated using a symbol received from an encoded data stream that includes a plurality of symbols. The decompression accelerator further to store the plurality of length codes in the first portion of the memory device in an order according to their respective number of bits.
摘要翻译：公开了一种集成电路，其包括包括第一部分和第二部分的存储器件。第一部分是具有第一组单元的第一类型的内容可寻址存储器（CAM），并且第二部分是具有第二组单元格的第二类型的CAM。第一组单元格小于第二组单元格。集成电路还包括耦合到存储器件的解压加速器，解压加速器以产生多个长度代码。多个长度码中的每一个包括至少一个位。使用从包括多个符号的编码数据流接收的符号来生成多个长度码。所述解压缩加速器进一步按照它们各自的位数按顺序将所述多个长度代码存储在所述存储器件的第一部分中。

9. 发明申请

US20150023500A1 APPARATUS AND METHOD FOR SKEIN HASHING 有权
标题翻译：装置和方法进行滑雪
公开(公告)号：US20150023500A1
公开(公告)日：2015-01-22
申请号：US14507427
申请日：2014-10-06
申请人： Farhana Sheikh , Jesse Walker , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Farhana Sheikh , Jesse Walker , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H04L9/08
CPC分类号： H04L9/0861 , H04L9/0618 , H04L9/0625 , H04L9/0631 , H04L9/0637 , H04L9/0643 , H04L9/0816 , H04L2209/125 , H04L2209/24 , H04N1/32277
摘要： Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
摘要翻译：这里描述了用于Skein散列的装置和方法。该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。

10. 发明授权

US08923510B2 Method and apparatus for efficiently implementing the advanced encryption standard 有权
标题翻译：有效实施高级加密标准的方法和装置
公开(公告)号：US08923510B2
公开(公告)日：2014-12-30
申请号：US11966658
申请日：2007-12-28
申请人： Shay Gueron , Michael E. Kounavis , Ram Krishnamurthy , Sanu K. Mathew
发明人： Shay Gueron , Michael E. Kounavis , Ram Krishnamurthy , Sanu K. Mathew
IPC分类号： H04L9/00 , G06F7/00
CPC分类号： H04L9/0631 , G06F7/00 , G06F9/30007 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30196 , G06F9/3887 , G06F21/602 , H04L2209/34
摘要： Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.
摘要翻译：公开了高级加密标准（AES）加密和解密过程的实现。在S盒处理的一个实施例中，转换16字节值的块，每个字节值从GF（256）中的多项式表示转换为GF（（22）4）中的多项式表示。对于GF（（22）4）中的每个对应多项式表示，计算GF（（22）4）中的乘法逆多项式表示。最后，对GF（（22）4）中的相应的乘法逆多项式表示进行转换，并应用仿射变换以在GF（256）中生成对应的多项式表示。在S盒处理的替代实施例中，计算多项式表示的幂并在GF（256）中相乘，以在GF（256）中生成乘法逆多项式表示。在反列混合的实施例中，将16字节值从GF（256）中的多项式表示转换为GF（（24）2）中的多项式表示。将四乘四矩阵应用于GF（（24）2）中的变换多项式表示，以实现反列混合。

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