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    • 3. 发明申请
    • Method for forming a contact in semiconductor device
    • 在半导体器件中形成接触的方法
    • US20050142886A1
    • 2005-06-30
    • US11026288
    • 2004-12-30
    • Kang LeeDate LeeKee Kim
    • Kang LeeDate LeeKee Kim
    • H01L21/28H01L21/302H01L21/306H01L21/311H01L21/461H01L21/768
    • H01L21/02063H01L21/02046H01L21/31116H01L21/76807H01L21/76814
    • A method for forming a contact hole in a semiconductor device is disclosed. The method for forming a contact hole in a semiconductor device comprises depositing a nitride layer and an ILD on a substrate including predetermined devices; forming a first photoresist pattern on the ILD and making a via hole by using the first photoresist pattern; performing a first ashing process; forming a second photoresist pattern on the ILD and making a trench using the second photoresist pattern; conducting a PET; performing a second ashing process and etching the predetermined portion of the nitride layer exposed through the via hole; and wet-cleaning the resulting structure. Accordingly, the present disclosure can fabricate a contact hole maximizing the characteristics of a semiconductor device just by performing a Post Etching Treatment after a trench is formed.
    • 公开了一种在半导体器件中形成接触孔的方法。 在半导体器件中形成接触孔的方法包括:在包括预定的器件的衬底上沉积氮化物层和ILD; 在ILD上形成第一光致抗蚀剂图案,并通过使用第一光致抗蚀剂图案形成通孔; 执行第一个灰化过程; 在所述ILD上形成第二光致抗蚀剂图案,并使用所述第二光致抗蚀剂图案形成沟槽; 进行PET; 执行第二灰化处理并蚀刻通过通孔露出的氮化物层的预定部分; 并湿法清洗所得到的结构。 因此,本公开可以仅在通过在形成沟槽之后执行后蚀刻处理来制造使半导体器件的特性最大化的接触孔。
    • 6. 发明申请
    • Analog buffer circuit for liquid crystal display device
    • 液晶显示装置的模拟缓冲电路
    • US20050001799A1
    • 2005-01-06
    • US10875733
    • 2004-06-25
    • Kee Kim
    • Kee Kim
    • G09G3/36
    • G09G3/3688G09G3/3696G09G2310/027G09G2310/0291G09G2330/021
    • An analog buffer circuit for a liquid crystal display (LCD) device includes a first capacitor and an inverter connected in series between an input terminal and an output terminal, a first reset switch connected between the input terminal and the first capacitor to reset the first capacitor, a first feedback switch connected to a first node between the first capacitor and the first reset switch, a second capacitor and a second feedback switch connected in series between a second node and a third node, the second node connected between the first capacitor and the inverter, and the third node connected between the inverter and the output terminal, a second reset switch connected between the second node and the third node to reset the inverter, and a third reset switch connected to a fourth node between the second capacitor and the second feedback switch to reset the second capacitor.
    • 一种用于液晶显示器(LCD)器件的模拟缓冲电路,包括串联连接在输入端和输出端之间的第一电容器和反相器,连接在输入端和第一电容器之间的第一复位开关,以复位第一电容器 连接到第一电容器和第一复位开关之间的第一节点的第一反馈开关,串联连接在第二节点和第三节点之间的第二电容器和第二反馈开关,第二节点连接在第一电容器和第二电容器之间, 逆变器和连接在逆变器和输出端子之间的第三节点,连接在第二节点和第三节点之间的第二复位开关以复位反相器;以及第三复位开关,连接到第二电容器和第二电容器之间的第四节点 反馈开关复位第二个电容。
    • 8. 发明申请
    • Error detecting circuit
    • 错误检测电路
    • US20060005091A1
    • 2006-01-05
    • US10882523
    • 2004-06-30
    • Subhasish MitraKee KimTak MakPrashant Goteti
    • Subhasish MitraKee KimTak MakPrashant Goteti
    • G01R31/28
    • G01R31/318541G01R31/31816G01R31/318566G11C2029/3202
    • In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.
    • 在一个实施例中,一种装置包括数据路径电路,用于响应于数据输入信号和至少第一数据时钟信号而产生数据输出信号; 阴影电路,耦合到数据路径电路,以在功能操作模式期间响应于数据输入信号和至少第二数据时钟信号产生阴影输出信号,并且响应于扫描信号产生扫描输出信号, 在测试操作模式期间的信号和至少第一测试时钟信号; 以及耦合到数据路径和阴影电路的误差检测电路,以响应于数据输出信号和阴影输出信号之间的失配而产生误差信号。