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1. 发明授权

US07681628B2 Dynamic control of back gate bias in a FinFET SRAM cell 失效
标题翻译： FinFET SRAM单元中背栅极偏置的动态控制
公开(公告)号：US07681628B2
公开(公告)日：2010-03-23
申请号：US11402400
申请日：2006-04-12
申请人： Rajiv V. Joshi , Keunwoo Kim , Edward J. Nowak , Richard Q. Williams
发明人： Rajiv V. Joshi , Keunwoo Kim , Edward J. Nowak , Richard Q. Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based on an operational mode (e.g., Read, Half-Select, Write, Standby) of the SRAM cell.
摘要翻译：本发明提供对FinFET SRAM单元中的上拉pFET的背栅极偏置的动态控制。根据本发明的方法包括向SRAM单元中的至少一个晶体管的背栅提供偏置电压，并且基于操作模式（例如，读取，半选择，写入，待机）动态地控制偏置电压，的SRAM单元。

2. 发明授权

US07198990B2 Method for making a FET channel 有权
标题翻译：制造FET通道的方法
公开(公告)号：US07198990B2
公开(公告)日：2007-04-03
申请号：US11137811
申请日：2005-05-24
申请人： Rajiv V. Joshi , Richard Q. Williams
发明人： Rajiv V. Joshi , Richard Q. Williams
IPC分类号： H01L21/335
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和Si x Ge 1-x x，其中78

3. 发明授权

US08835261B2 Field effect transistor structure and method of forming same 有权
标题翻译：场效应晶体管结构及其形成方法
公开(公告)号：US08835261B2
公开(公告)日：2014-09-16
申请号：US13046902
申请日：2011-03-14
申请人： Edward J. Nowak , Richard Q. Williams
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L21/31
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.
摘要翻译：本公开一般涉及金属氧化物半导体场效应晶体管（MOSFET）结构及其形成方法。 MOSFET结构在衬底上包括至少一个半导体本体; 在所述至少一个半导体主体的顶表面上的电介质盖，其中所述至少一个半导体本体的宽度小于所述电介质盖的宽度; 保护地涂覆所述至少一个半导体主体的栅介质层; 以及栅极电介质层上的至少一个导电栅极。

4. 发明授权

US08119474B2 High performance capacitors in planar back gates CMOS 有权
标题翻译：平面后门CMOS中的高性能电容器
公开(公告)号：US08119474B2
公开(公告)日：2012-02-21
申请号：US12688243
申请日：2010-01-15
申请人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
发明人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.
摘要翻译：一种双栅极CMOS结构的制造方法和器件。该结构包括绝缘层中的第一板和与第一板电对应的绝缘层之上的第二板。隔离结构在第一板和第二板之间。

5. 发明授权

US07572724B2 Doped single crystal silicon silicided eFuse 有权
标题翻译：掺杂单晶硅硅片eFuse
公开(公告)号：US07572724B2
公开(公告)日：2009-08-11
申请号：US12043226
申请日：2008-03-06
申请人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
发明人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/00
CPC分类号： H01L27/10 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.
摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。将单晶硅层图案化成条带。在构图之前或之后，单晶硅层掺杂有一种或多种杂质。至少单晶硅层的上部然后被硅化以形成硅化带。在一个实施例中，整个单晶硅带被硅化以产生硅化物条。在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。上覆的硅化物材料允许熔丝作为未编程状态的导体。然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

6. 发明申请

US20080164535A1 CURVED FINFETS 有权
标题翻译：弯曲的熔体
公开(公告)号：US20080164535A1
公开(公告)日：2008-07-10
申请号：US11621228
申请日：2007-01-09
申请人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
发明人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/66795 , H01L29/7843
摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.
摘要翻译：一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的移动，中央部分不能自由移动。在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

7. 发明申请

US20080020531A1 SEMICONDUCTOR DEVICES HAVING TORSIONAL STRESSES 失效
标题翻译：具有扭转应力的半导体器件
公开(公告)号：US20080020531A1
公开(公告)日：2008-01-24
申请号：US11458461
申请日：2006-07-19
申请人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
发明人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/7624 , H01L21/823807 , H01L29/66795 , H01L29/7846 , H01L29/7848 , H01L29/785
摘要： A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of the FET. In a particular embodiment, a second stressor element is provided at or near an opposite corner of the active semiconductor region to apply a stress in a second direction to an opposite side of a channel region of the FET, the second direction being opposite to the first direction. In this way, the first and second stressor elements cooperate together in applying a torsional stress to the channel region of the FET.
摘要翻译：提供了一种FET结构，其中设置在有源半导体区域的一个角附近或附近的至少一个应激元件将第一方向上的应力施加到FET的沟道区域的一侧，以向该沟道区域的沟道区域施加扭转应力 FET。在特定实施例中，第二应力元件设置在有源半导体区域的相对拐角处或附近，以将第二方向上的应力施加到FET的沟道区域的相对侧，第二方向与第一方向相反方向。以这种方式，第一和第二应激元件协同工作，将扭曲应力施加到FET的沟道区域。

8. 发明授权

US07786466B2 Carbon nanotube based integrated semiconductor circuit 失效
标题翻译：碳纳米管集成半导体电路
公开(公告)号：US07786466B2
公开(公告)日：2010-08-31
申请号：US11972669
申请日：2008-01-11
申请人： Joerg Appenzeller , AJ Kleinosowski , Edward J. Nowak , Richard Q. Williams
发明人： Joerg Appenzeller , AJ Kleinosowski , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L51/00
CPC分类号： H01L51/0541 , B82Y10/00 , H01L27/11 , H01L27/1104 , H01L27/283 , H01L51/0048 , H01L51/0558 , Y10S977/742 , Y10S977/75 , Y10S977/751 , Y10S977/752
摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.
摘要翻译：在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过介电层在两个器件区域之间电气偏置区域碳纳米管。碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

9. 发明申请

US20080185644A1 FETS WITH SELF-ALIGNED BODIES AND BACKGATE HOLES 有权
标题翻译：具有自对准体和背部孔的FET
公开(公告)号：US20080185644A1
公开(公告)日：2008-08-07
申请号：US11539288
申请日：2006-10-06
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Richard Q. Williams
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78612 , H01L29/66772 , H01L29/78621 , H01L29/78648
摘要： A FET has a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.
摘要翻译： FET具有浅电源/漏极区域，深沟道区域，栅极堆叠和被电介质包围的背栅极。 FET结构还包括延伸通过通道区域的整个深度的晕或凹坑植入物。因为沟道的一部分光晕和阱掺杂比源极/漏极深度更深，所以实现了更好的阈值电压和过程控制。还提供了后栅化FET结构，其具有在该结构中的第一介电层，其在沟道区域和后栅极之间的浅源极/漏极区域下方延伸。该第一电介质层从背栅的两侧的源极/漏极区下方延伸并与第二电介质接触，使得后栅极在每一侧上界定或通过电介质隔离。

10. 发明授权

US07345334B2 Integrated circuit (IC) with high-Q on-chip discrete capacitors 失效
标题翻译：集成电路（IC）与高Q片上分立电容
公开(公告)号：US07345334B2
公开(公告)日：2008-03-18
申请号：US10908081
申请日：2005-04-27
申请人： Edward J. Nowak , Richard Q. Williams
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L29/72
CPC分类号： H01L27/1203 , H01L27/0805 , H01L29/94
摘要： A semiconductor structure that may be a discrete capacitor, a Silicon On Insulator (SOI) Integrated Circuit (IC) including circuits with discrete such capacitors and/or decoupled by such discrete capacitors and an on-chip decoupling capacitor (decap). One capacitor plate may be a well (N-well or P-well) in a silicon bulk layer or a thickened portion of a surface silicon layer. The other capacitor plate may be doped polysilicon and separated from the first capacitor plate by capacitor dielectric, e.g., CVD or thermal oxide. Contacts to each of the capacitor plates directly connect and extend from the respective plates, such that direct contact is available from both plates.
摘要翻译：可以是分立电容器的半导体结构，包括具有离散这种电容器的电路和/或由这种分立电容器去耦合的片上绝缘体（SOI）集成电路（IC）和片上去耦电容器（decap））。一个电容器板可以是硅本体层中的阱（N阱或P阱）或表面硅层的增厚部分。另一个电容器板可以是掺杂多晶硅并且通过电容器电介质例如CVD或热氧化物与第一电容器板分离。与每个电容器板的接触件从相应的板直接连接和延伸，使得从两个板可以直接接触。

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