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1. 发明申请

US20080164535A1 CURVED FINFETS 有权
标题翻译：弯曲的熔体
公开(公告)号：US20080164535A1
公开(公告)日：2008-07-10
申请号：US11621228
申请日：2007-01-09
申请人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
发明人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/66795 , H01L29/7843
摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.
摘要翻译：一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的移动，中央部分不能自由移动。在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

2. 发明授权

US07538391B2 Curved FINFETs 有权
标题翻译：弯曲的FINFET
公开(公告)号：US07538391B2
公开(公告)日：2009-05-26
申请号：US11621228
申请日：2007-01-09
申请人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
发明人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/66795 , H01L29/7843
摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.
摘要翻译：一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的移动，中央部分不能自由移动。在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

3. 发明申请

US20080020531A1 SEMICONDUCTOR DEVICES HAVING TORSIONAL STRESSES 失效
标题翻译：具有扭转应力的半导体器件
公开(公告)号：US20080020531A1
公开(公告)日：2008-01-24
申请号：US11458461
申请日：2006-07-19
申请人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
发明人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/7624 , H01L21/823807 , H01L29/66795 , H01L29/7846 , H01L29/7848 , H01L29/785
摘要： A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of the FET. In a particular embodiment, a second stressor element is provided at or near an opposite corner of the active semiconductor region to apply a stress in a second direction to an opposite side of a channel region of the FET, the second direction being opposite to the first direction. In this way, the first and second stressor elements cooperate together in applying a torsional stress to the channel region of the FET.
摘要翻译：提供了一种FET结构，其中设置在有源半导体区域的一个角附近或附近的至少一个应激元件将第一方向上的应力施加到FET的沟道区域的一侧，以向该沟道区域的沟道区域施加扭转应力 FET。在特定实施例中，第二应力元件设置在有源半导体区域的相对拐角处或附近，以将第二方向上的应力施加到FET的沟道区域的相对侧，第二方向与第一方向相反方向。以这种方式，第一和第二应激元件协同工作，将扭曲应力施加到FET的沟道区域。

4. 发明授权

US07462916B2 Semiconductor devices having torsional stresses 失效
标题翻译：具有扭转应力的半导体器件
公开(公告)号：US07462916B2
公开(公告)日：2008-12-09
申请号：US11458461
申请日：2006-07-19
申请人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
发明人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
IPC分类号： H01L29/76
CPC分类号： H01L29/78 , H01L21/7624 , H01L21/823807 , H01L29/66795 , H01L29/7846 , H01L29/7848 , H01L29/785
摘要： A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of the FET. In a particular embodiment, a second stressor element is provided at or near an opposite corner of the active semiconductor region to apply a stress in a second direction to an opposite side of a channel region of the FET, the second direction being opposite to the first direction. In this way, the first and second stressor elements cooperate together in applying a torsional stress to the channel region of the FET.
摘要翻译：提供了一种FET结构，其中设置在有源半导体区域的一个角附近或附近的至少一个应激元件将第一方向上的应力施加到FET的沟道区域的一侧，以向该沟道区域的沟道区域施加扭转应力 FET。在特定实施例中，第二应力元件设置在有源半导体区域的相对拐角处或附近，以将第二方向上的应力施加到FET的沟道区域的相对侧，第二方向与第一方向相反方向。以这种方式，第一和第二应激元件协同工作，将扭曲应力施加到FET的沟道区域。

5. 发明授权

US08617412B2 Nano-filter and method of forming same, and method of filtration 失效
标题翻译：纳米过滤器及其形成方法及过滤方法
公开(公告)号：US08617412B2
公开(公告)日：2013-12-31
申请号：US12966370
申请日：2010-12-13
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
IPC分类号： C23F3/00 , B01D29/46 , H01L21/02
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译：本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。纳米线结构可以包括多个垂直堆叠的水平纳米线。

6. 发明授权

US07517806B2 Integrated circuit having pairs of parallel complementary FinFETs 失效
标题翻译：具有成对的并联互补FinFET的集成电路
公开(公告)号：US07517806B2
公开(公告)日：2009-04-14
申请号：US11186748
申请日：2005-07-21
申请人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
发明人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
IPC分类号： H01L21/302
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

7. 发明申请

US20120145650A1 NANO-FILTER AND METHOD OF FORMING SAME, AND METHOD OF FILTRATION 失效
标题翻译：纳滤器及其形成方法，以及过滤方法
公开(公告)号：US20120145650A1
公开(公告)日：2012-06-14
申请号：US12966370
申请日：2010-12-13
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
IPC分类号： B01D35/28 , B01D37/00 , B01D35/30 , B82Y5/00 , B82Y40/00
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译：本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。纳米线结构可以包括多个垂直堆叠的水平纳米线。

8. 发明授权

US06943405B2 Integrated circuit having pairs of parallel complementary FinFETs 有权
标题翻译：具有成对的并联互补FinFET的集成电路
公开(公告)号：US06943405B2
公开(公告)日：2005-09-13
申请号：US10604206
申请日：2003-07-01
申请人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
发明人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
IPC分类号： H01L21/308 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/00 , H01L29/76
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

9. 发明授权

US07981772B2 Methods of fabricating nanostructures 失效
标题翻译：制造纳米结构的方法
公开(公告)号：US07981772B2
公开(公告)日：2011-07-19
申请号：US12344696
申请日：2008-12-29
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
IPC分类号： H01L21/3213
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0669 , H01L29/0673 , H01L29/16 , H01L29/161 , Y10S977/888
摘要： A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the SiX material. The method further includes etching the SiX material to expose portions of the Si material and etching the exposed portions of the Si material. The method also includes breaking away the Si material to form silicon nanowires.
摘要翻译：示出了制造纳米结构的方法，更具体地说，涉及制造硅纳米线的方法。制造纳米线的方法包括在衬底上形成SiX材料和材料Si的夹层结构，并蚀刻夹层结构以暴露Si材料和SiX材料的侧壁。该方法还包括蚀刻SiX材料以暴露Si材料的部分并蚀刻Si材料的暴露部分。该方法还包括分离Si材料以形成硅纳米线。

10. 发明申请

US20110263101A1 CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT 失效
标题翻译：基于碳纳米管的集成半导体电路
公开(公告)号：US20110263101A1
公开(公告)日：2011-10-27
申请号：US13170525
申请日：2011-06-28
申请人： Joerg Appenzeller , AJ Kleinosowski , Edward J. Nowak , Richard Q. Williams
发明人： Joerg Appenzeller , AJ Kleinosowski , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/20 , B82Y40/00
CPC分类号： H01L51/0541 , B82Y10/00 , H01L27/11 , H01L27/1104 , H01L27/283 , H01L51/0048 , H01L51/0558 , Y10S977/742 , Y10S977/75 , Y10S977/751 , Y10S977/752
摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.
摘要翻译：在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过电介质层对两个器件区域之间的电介质层进行电偏置碳纳米管。碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

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