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1. 发明授权

US07405521B2 Multiple frequency plasma processor method and apparatus 有权
标题翻译：多频等离子体处理器的方法和装置
公开(公告)号：US07405521B2
公开(公告)日：2008-07-29
申请号：US10645665
申请日：2003-08-22
申请人： Raj Dhindsa , S. M. Reza Sadjadi , Felix Kozakevich , Dave Trussell , Lumin Li , Eric Lenz , Camelia Rusu , Mukund Srinivasan , Aaron Eppler , Jim Tietz , Jeffrey Marks
发明人： Raj Dhindsa , S. M. Reza Sadjadi , Felix Kozakevich , Dave Trussell , Lumin Li , Eric Lenz , Camelia Rusu , Mukund Srinivasan , Aaron Eppler , Jim Tietz , Jeffrey Marks
IPC分类号： H01J7/24 , C23F1/00 , C23C16/00
CPC分类号： H01J37/32174 , H01J37/32082 , H01J37/32165
摘要： A workpiece is processed with a plasma in a vacuum plasma processing chamber by exciting the plasma at several frequencies such that the excitation of the plasma by the several frequencies simultaneously causes several different phenomena to occur in the plasma. The chamber includes central top and bottom electrodes and a peripheral top and/or bottom electrode arrangement that is either powered by RF or is connected to a reference potential by a filter arrangement that passes at least one of the plasma excitation frequencies to the exclusion of other frequencies.
摘要翻译：通过以几个频率激发等离子体，在真空等离子体处理室中用等离子体处理工件，使得等离子体被几个频率激发同时导致在等离子体中发生几种不同的现象。该腔室包括中央顶部和底部电极以及由RF供电的外围顶部和/或底部电极装置，或通过将至少一个等离子体激发频率传递至排除另一个等离子体激发频率的滤波器装置连接到参考电位频率

2. 发明授权

US07977242B2 Double mask self-aligned double patterning technology (SADPT) process 有权
标题翻译：双面膜自对准双图案技术（SADPT）工艺
公开(公告)号：US07977242B2
公开(公告)日：2011-07-12
申请号：US12366113
申请日：2009-02-05
申请人： S. M. Reza Sadjadi , Lumin Li , Andrew R. Romano
发明人： S. M. Reza Sadjadi , Lumin Li , Andrew R. Romano
IPC分类号： H01L21/461 , H01L21/311
CPC分类号： H01L21/0337
摘要： A method for providing features in an etch layer is provided by forming an organic mask layer over the inorganic mask layer, forming a silicon-containing mask layer over the organic mask layer, forming a patterned mask layer over the silicon-containing mask layer, etching the silicon-containing mask layer through the patterned mask, depositing a polymer over the etched silicon-containing mask layer, depositing a silicon-containing film over the polymer, planarizing the silicon-containing film, selectively removing the polymer leaving the silicon-containing film, etching the organic layer, and etching the inorganic layer.
摘要翻译：通过在无机掩模层上形成有机掩模层，在有机掩模层上形成含硅掩模层，在含硅掩模层上形成图案化掩模层，蚀刻，提供蚀刻层中提供特征的方法通过图案化掩模的含硅掩模层，在蚀刻的含硅掩模层上沉积聚合物，在聚合物上沉积含硅膜，平坦化含硅膜，选择性地除去离开含硅膜的聚合物蚀刻有机层，并蚀刻无机层。

3. 发明申请

US20090215272A1 DOUBLE MASK SELF-ALIGNED DOUBLE PATTERNING TECHNOLOGY (SADPT) PROCESS 有权
标题翻译：双面掩模自对准双模式技术（SADPT）工艺
公开(公告)号：US20090215272A1
公开(公告)日：2009-08-27
申请号：US12366113
申请日：2009-02-05
申请人： S. M. Reza Sadjadi , Lumin Li , Andrew R. Romano
发明人： S. M. Reza Sadjadi , Lumin Li , Andrew R. Romano
IPC分类号： H01L21/308
CPC分类号： H01L21/0337
摘要： A method for providing features in an etch layer is provided by forming an organic mask layer over the inorganic mask layer, forming a silicon-containing mask layer over the organic mask layer, forming a patterned mask layer over the silicon-containing mask layer, etching the silicon-containing mask layer through the patterned mask, depositing a polymer over the etched silicon-containing mask layer, depositing a silicon-containing film over the polymer, planarizing the silicon-containing film, selectively removing the polymer leaving the silicon-containing film, etching the organic layer, and etching the inorganic layer.
摘要翻译：通过在无机掩模层上形成有机掩模层，在有机掩模层上形成含硅掩模层，在含硅掩模层上形成图案化掩模层，蚀刻，提供蚀刻层中提供特征的方法通过图案化掩模的含硅掩模层，在蚀刻的含硅掩模层上沉积聚合物，在聚合物上沉积含硅膜，平坦化含硅膜，选择性地除去离开含硅膜的聚合物蚀刻有机层，并蚀刻无机层。

4. 发明授权

US07429533B2 Pitch reduction 有权
标题翻译：节距减少
公开(公告)号：US07429533B2
公开(公告)日：2008-09-30
申请号：US11432194
申请日：2006-05-10
申请人： Zhisong Huang , Jeffrey Marks , S. M. Reza Sadjadi
发明人： Zhisong Huang , Jeffrey Marks , S. M. Reza Sadjadi
IPC分类号： H01L21/311 , H01L21/306
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139
摘要： A method for providing features in an etch layer is provided. A sacrificial patterned layer with sacrificial features is provided over an etch layer. Conformal sidewalls are formed in the sacrificial features, comprising at least two cycles of a sidewall formation process, wherein each cycle comprises a sidewall deposition phase and a sidewall profile shaping phase. Parts of the sacrificial patterned layer between conformal sidewalls are removed leaving the conformal sidewalls with gaps between the conformal sidewalls where parts of the sacrificial patterned layer were selectively removed. Features are etched in the etch layer using the conformal sidewalls as an etch mask, wherein the features in the etch layer are etched through the gaps between the conformal sidewalls where parts of the sacrificial patterned layer were selectively removed.
摘要翻译：提供了一种用于在蚀刻层中提供特征的方法。在蚀刻层上提供具有牺牲特征的牺牲图案层。保形侧壁形成在牺牲特征中，包括侧壁形成工艺的至少两个循环，其中每个循环包括侧壁沉积阶段和侧壁轮廓成形阶段。除去共形侧壁之间的牺牲图案层的部分，留下保形侧壁，其中保形侧壁之间的间隙被选择性地去除牺牲图案层的部分。使用保形侧壁作为蚀刻掩模在蚀刻层中蚀刻特征，其中蚀刻层中的特征被蚀刻通过牺牲图案层的部分被选择性去除的共形侧壁之间的间隙。

5. 发明授权

US07271107B2 Reduction of feature critical dimensions using multiple masks 有权
标题翻译：使用多个掩模降低功能关键尺寸
公开(公告)号：US07271107B2
公开(公告)日：2007-09-18
申请号：US11050985
申请日：2005-02-03
申请人： Jeffrey Marks , S. M. Reza Sadjadi
发明人： Jeffrey Marks , S. M. Reza Sadjadi
IPC分类号： H01L21/311
CPC分类号： H01L21/0273 , H01L21/3088 , H01L21/31144 , H01L21/32139
摘要： A method for forming features in an etch layer is provided. A first mask is formed over the etch layer wherein the first mask defines a plurality of spaces with widths. A sidewall layer is formed over the first mask. Features are etched into the etch layer through the sidewall layer, wherein the features have widths that are smaller than the widths of the spaces defined by the first mask. The mask and sidewall layer are removed. An additional mask is formed over the etch layer wherein the additional mask defines a plurality of spaces with widths. A sidewall layer is formed over the additional mask. Features are etched into the etch layer through the sidewall layer, wherein the widths that are smaller than the widths of the spaces defined by the first mask. The mask and sidewall layer are removed.
摘要翻译：提供了一种在蚀刻层中形成特征的方法。在蚀刻层上形成第一掩模，其中第一掩模限定具有宽度的多个空间。在第一掩模上形成侧壁层。特征通过侧壁蚀刻到蚀刻层中，其中特征具有小于由第一掩模限定的空间的宽度的宽度。去除掩模和侧壁层。在蚀刻层上形成另外的掩模，其中附加掩模限定具有宽度的多个空间。侧壁层形成在附加掩模上。特征通过侧壁蚀刻到蚀刻层中，其中宽度小于由第一掩模限定的空间的宽度。去除掩模和侧壁层。

6. 发明授权

US08268118B2 Critical dimension reduction and roughness control 有权
标题翻译：关键尺寸减小和粗糙度控制
公开(公告)号：US08268118B2
公开(公告)日：2012-09-18
申请号：US12711420
申请日：2010-02-24
申请人： Sangheon Lee , Dae-Han Choi , Jisoo Kim , Peter Cirigliano , Zhisong Huang , Robert Charatan , S. M. Reza Sadjadi
发明人： Sangheon Lee , Dae-Han Choi , Jisoo Kim , Peter Cirigliano , Zhisong Huang , Robert Charatan , S. M. Reza Sadjadi
IPC分类号： H01L21/3065
CPC分类号： C23F4/00 , H01L21/31116 , H01L21/31144 , H01L21/76816 , Y10S438/947
摘要： A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.
摘要翻译：提供了一种在蚀刻层中形成特征的方法。在蚀刻层上形成光致抗蚀剂层。图案化光致抗蚀剂层以形成具有光致抗蚀剂侧壁的光致抗蚀剂特征。在光致抗蚀剂层和光致抗蚀剂特征的底部上形成控制层。在光致抗蚀剂特征和控制层的侧壁上沉积保形层以减少光刻胶特征的临界尺寸。控制层的开口打开，控制层突破性化学。特征被蚀刻到蚀刻层中，其蚀刻化学性质不同于控制层突破性化学，其中控制层比蚀刻化学性质比共形层更耐蚀刻蚀刻。

7. 发明授权

US08172980B2 Device with self aligned gaps for capacitance reduction 有权
标题翻译：具有自对准间隙的器件，用于降低电容
公开(公告)号：US08172980B2
公开(公告)日：2012-05-08
申请号：US12202043
申请日：2008-08-29
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： C23F1/00 , H01L21/306 , C23C16/00
CPC分类号： H01L21/7682 , H01J37/32623 , H01J37/32633 , H01J37/32642 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
摘要翻译：提供了用于降低半导体器件布线之间的电容的方法。在电介质层上形成牺牲层。多个特征被蚀刻到牺牲层和电介质层中。功能填充填充材料。去除牺牲层，使得填充材料的部分保持暴露在电介质层的表面之上，其中空间位于填充材料的暴露部分之间，其中空间在先前被牺牲层占据的区域中。填充材料部分之间的间隙的宽度随收缩侧壁沉积而收缩。通过收缩侧壁沉积将间隙蚀刻到介电层中。去除填充材料和收缩侧壁沉积。

8. 发明授权

US07772122B2 Sidewall forming processes 有权
标题翻译：侧壁成型工艺
公开(公告)号：US07772122B2
公开(公告)日：2010-08-10
申请号：US12233517
申请日：2008-09-18
申请人： Peter Cirigliano , Helen Zhu , Ji Soo Kim , S. M. Reza Sadjadi
发明人： Peter Cirigliano , Helen Zhu , Ji Soo Kim , S. M. Reza Sadjadi
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/31144 , H01L21/312
摘要： An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on the patterned photoresist mask by performing multiple cyclical depositions. Each cyclical deposition involves at least a depositing phase for depositing a deposition layer over surfaces of the patterned photoresist mask and a profile shaping phase for shaping vertical surfaces in the deposition layer. Each sidewall forming process further comprises a breakthrough etch for selectively etching horizontal surfaces of the protective layer with respect to vertical surfaces of the protective layer. Afterwards, the etch layer is etched to form a feature having a critical dimension that is less than the critical dimension of the features in the patterned photoresist mask.
摘要翻译：提供了图案化光刻胶掩模下面的蚀刻层。执行多个侧壁形成工序。每个侧壁形成工艺包括通过执行多个循环沉积在图案化的光致抗蚀剂掩模上沉积保护层。每个循环沉积涉及至少沉积阶段，用于在图案化的光致抗蚀剂掩模的表面上沉积沉积层，以及用于在沉积层中形成垂直表面的轮廓成形阶段。每个侧壁形成工艺还包括用于相对于保护层的垂直表面选择性地蚀刻保护层的水平表面的穿透蚀刻。之后，刻蚀蚀刻层以形成临界尺寸小于图案化光致抗蚀剂掩模中特征的临界尺寸的特征。

9. 发明授权

US07491647B2 Etch with striation control 失效
标题翻译：蚀刻与条纹控制
公开(公告)号：US07491647B2
公开(公告)日：2009-02-17
申请号：US11223363
申请日：2005-09-09
申请人： S. M. Reza Sadjadi , Peter Cirigliano , Ji Soo Kim , Zhisong Huang , Eric A. Hudson
发明人： S. M. Reza Sadjadi , Peter Cirigliano , Ji Soo Kim , Zhisong Huang , Eric A. Hudson
IPC分类号： H01L21/311
CPC分类号： H01L21/0273 , H01L21/0274 , H01L21/31144 , H01L21/76802 , Y10S438/942 , Y10S438/949
摘要： A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.
摘要翻译：提供了蚀刻蚀刻层中的特征的方法。在具有侧壁的光致抗蚀剂特征的蚀刻层上形成图案化的光致抗蚀剂掩模，其中光致抗蚀剂特征的侧壁具有形成峰和谷的条纹。光致抗蚀剂特征的侧壁的条纹减小。减小条纹包括至少一个周期，其中每个周期包括蚀刻由光致抗蚀剂特征的侧壁的条纹形成的峰，并沉积在光致抗蚀剂特征的侧壁上。通过光致抗蚀剂特征将特征蚀刻到蚀刻层中。去除光致抗蚀剂掩模。

10. 发明授权

US07432189B2 Device with self aligned gaps for capacitance reduction 有权
标题翻译：具有自对准间隙的器件，用于降低电容
公开(公告)号：US07432189B2
公开(公告)日：2008-10-07
申请号：US11291672
申请日：2005-11-30
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01J37/32623 , H01J37/32633 , H01J37/32642 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
摘要翻译：提供了用于降低半导体器件布线之间的电容的方法。在电介质层上形成牺牲层。多个特征被蚀刻到牺牲层和电介质层中。功能填充填充材料。去除牺牲层，使得填充材料的部分保持暴露在电介质层的表面之上，其中空间位于填充材料的暴露部分之间，其中空间在先前被牺牲层占据的区域中。填充材料部分之间的间隙的宽度随收缩侧壁沉积而收缩。通过收缩侧壁沉积将间隙蚀刻到介电层中。去除填充材料和收缩侧壁沉积。

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