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1. 发明授权

US6141734A Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol 失效
标题翻译：用于在写入无效协议的上下文中优化LDxL和STxC互锁指令的性能的方法和装置
公开(公告)号：US6141734A
公开(公告)日：2000-10-31
申请号：US17752
申请日：1998-02-03
申请人： Rahul Razdan , David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer , Daniel Lawrence Leibholz
发明人： Rahul Razdan , David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer , Daniel Lawrence Leibholz
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A technique for implementing load-locked and store-conditional instruction primitives by using a local cache for information about exclusive ownership. The valid bit in particular provides information to properly execute load-locked and store-conditional instructions without the need for lock flag or local lock address registers for each individual locked address. Integrity of locked data is accomplished by insuring that load-locked and store-conditional instructions are processed in order, that no internal agents can evict blocks from a local cache as a side effect as their processing, that external agents update the context of cache memories first using invalidating probe commands, and that only non-speculative instructions are permitted to generate external commands.
摘要翻译：一种用于通过使用本地缓存来获取关于独占所有权的信息来实现加载锁定和存储条件指令原语的技术。有效位特别提供了正确执行加载锁定和存储条件指令的信息，而不需要锁定标志或每个单独锁定地址的本地锁定地址寄存器。锁定数据的完整性通过确保按顺序处理加载锁定和存储条件指令来实现，即内部代理可以将本地缓存中的块作为其处理的副作用来驱逐块，外部代理更新缓存存储器的上下文首先使用无效探测命令，并且只允许非推测性指令生成外部命令。

2. 发明授权

US5924120A Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times 失效
$Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times$
标题翻译：在内部处理器总线的上下文中最大化利用率的方法和装置，其运行速度大于内部事务时间
公开(公告)号：US5924120A
公开(公告)日：1999-07-13
申请号：US18320
申请日：1998-02-03
申请人： Rahul Razdan , David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
发明人： Rahul Razdan , David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
IPC分类号： G06F9/38 , G06F12/08 , G06F9/40 , G06F12/04
CPC分类号： G06F12/0897 , G06F9/3869
摘要： Use of an internal processor data bus is maximized in a system where external transactions may occur at a rate which is fractionally slower than the rate of the internal transactions. The technique inserts a selectable delay element in the signal path during an external operation such as a cache fill operation. The one cycle delay provides a time slot in which an internal operation, such as a load from an internal cache, may be performed. This technique therefore permits full use of the time slots on the internal data bus. It can, for, example, allow load operations to begin at a much earlier time than would otherwise be possible in architectures where fill operations can consume multiple bus time slots.
摘要翻译：在内部处理器数据总线的使用最大化的系统中，外部事务可能以比内部事务的速度慢的速度发生。该技术在诸如高速缓存填充操作的外部操作期间在信号路径中插入可选择的延迟元件。一个周期延迟提供了可以执行内部操作（例如来自内部高速缓存的负载）的时隙。因此，该技术允许充分利用内部数据总线上的时隙。例如，它可以允许加载操作在比填充操作可以消耗多个总线时隙的体系结构中更早的时间开始。

3. 发明授权

US07093105B2 Method and apparatus for determining availability of a queue to which a program step is issued out of program order 有权
标题翻译：用于确定从程序顺序发出程序步骤的队列的可用性的方法和装置
公开(公告)号：US07093105B2
公开(公告)日：2006-08-15
申请号：US10779503
申请日：2004-02-13
申请人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
发明人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
IPC分类号： G06F9/30
CPC分类号： G06F7/76 , G06F7/4824 , G06F7/508 , G06F7/535 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F2207/5352
摘要： A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (value) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.
摘要翻译：允许以非程序顺序将发布队列中的程序步骤发送到执行队列的方法和装置通过允许在需要的资源变得可用时执行程序顺序步骤来减少停止。该方法使用模数运算来对执行队列中的位置进行预分配，并使条目保持正确的程序顺序。该方法使用附加位来表示模块结果（值），并且还可以利用加载存储器号映射存储器来增加执行速度。通过这样的布置，由于等待当前指令的所需资源（即，存储器或总线）可用性，计算机系统可以通过发出存储器或总线资源可用的指令来减少丢失的性能，即使该指令不是下一个在原程序中。因此，本发明允许存储器参考指令在资源可用时发布。

4. 发明授权

US06738896B1 Method and apparatus for determining availability of a queue which allows random insertion 失效
标题翻译：用于确定允许随机插入的队列的可用性的方法和装置
公开(公告)号：US06738896B1
公开(公告)日：2004-05-18
申请号：US09495190
申请日：2000-01-31
申请人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
发明人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
IPC分类号： G06F930
CPC分类号： G06F7/76 , G06F7/4824 , G06F7/508 , G06F7/535 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F2207/5352
摘要： A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (valve) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.
摘要翻译：允许以非程序顺序将发布队列中的程序步骤发送到执行队列的方法和装置通过允许在需要的资源变得可用时执行程序顺序步骤来减少停止。该方法使用模数运算来对执行队列中的位置进行预分配，并使条目保持正确的程序顺序。该方法使用额外的位来表示模块结果（阀），并且还可以利用加载存储器号码映射存储器来增加执行速度。通过这样的布置，由于等待当前指令的所需资源（即存储器或总线）可用性，计算机系统可以通过发出存储器或总线资源可用的指令来减少丢失的性能，即使该指令不是下一个在原程序中。因此，本发明允许存储器参考指令在资源可用时发布。

5. 发明授权

US08025240B2 Radiant heat flooring system 有权
标题翻译：辐射热地板系统
公开(公告)号：US08025240B2
公开(公告)日：2011-09-27
申请号：US11550977
申请日：2006-10-19
申请人： James Keller
发明人： James Keller
IPC分类号： F24D3/14 , F24D3/12
CPC分类号： F24D3/127 , F24D3/142
摘要： A flooring system for radiant heating includes a top floor portion and a subfloor portion. The top portion is releasably connectable to the subfloor portion in a vertical direction substantially perpendicular to a walking surface of the top portion. The top portion includes a bottom side and top channel portion downwardly depending from the bottom side. The subfloor portion includes a top side and a bottom channel portion extending upwardly from the top side. The top channel portion and the bottom channel portion bound a channel for receiving a heating conduit. The channel extends longitudinally relative to the top floor portion and the subfloor portion.
摘要翻译：用于辐射加热的地板系统包括顶层部分和底层地板部分。顶部可在基本上垂直于顶部的行走表面的垂直方向上可释放地连接到底层地板部分。顶部包括从底侧向下悬垂的底侧和顶部通道部分。底层部分包括从顶侧向上延伸的顶侧和底通道部分。顶部通道部分和底部通道部分限定了用于接收加热导管的通道。通道相对于顶层部分和底层部分纵向延伸。

6. 发明授权

US07346078B2 Processing of received data within a multiple processor device 有权
标题翻译：处理多处理器设备内的接收数据
公开(公告)号：US07346078B2
公开(公告)日：2008-03-18
申请号：US10356324
申请日：2003-01-31
申请人： Manu Gulati , Laurent Moll , James Keller
发明人： Manu Gulati , Laurent Moll , James Keller
IPC分类号： H04J3/22
CPC分类号： G06F13/4247
摘要： A multiple processor device stores a stream of data as a plurality of data segments, which includes multiplexed data fragments from at least one of a plurality of virtual channels. The data segments that comprise the stream of data correspond to the multiplexed data fragments from the virtual channels. The multiple processor device then decodes at least one data segment in accordance with one of a plurality of transmission protocols to produce a decoded data segment. The multiple processor device then stores the decoded data segment to align it in accordance with a data path segment size. The multiple processor device then interprets the stored decoded data segment with respect to a corresponding one of the plurality of virtual channels to determine a destination of the stored decoded data segment. The multiple processor device then stores the decoded data segment as part of reassembled data.
摘要翻译：多处理器设备将数据流存储为多个数据段，其包括来自多个虚拟通道中的至少一个的多路复用数据片段。构成数据流的数据段对应于来自虚拟通道的复用数据片段。多处理器设备然后根据多个传输协议之一对至少一个数据段进行解码，以产生解码的数据段。然后，多处理器设备存储解码的数据段，以根据数据路径段大小进行对准。然后，多处理器设备相对于多个虚拟通道中的相应一个解码存储的解码数据段，以确定存储的解码数据段的目的地。然后，多处理器设备将解码的数据段存储为重新组装的数据的一部分。

7. 发明申请

US20070271402A1 Partially Populated, Hierarchical Crossbar 有权
标题翻译：部分填充，分层交叉
公开(公告)号：US20070271402A1
公开(公告)日：2007-11-22
申请号：US11832841
申请日：2007-08-02
申请人： Sridhar Subramanian , James Keller , George Yiu , Ruchi Wadhawan
发明人： Sridhar Subramanian , James Keller , George Yiu , Ruchi Wadhawan
IPC分类号： G06F13/00
CPC分类号： G06F13/364 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.
摘要翻译：在各种实施例中，装置包括多个代理和互连。在一个实施方案中，多种试剂包括第一至第四试剂。互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还包括在从第三代理到第四代理的第二通信路径中。在另一实施例中，每个段由选择电路驱动。至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

8. 发明授权

US08962808B2 EGFR-related polypeptides and methods of use 有权
标题翻译： EGFR相关多肽和使用方法
公开(公告)号：US08962808B2
公开(公告)日：2015-02-24
申请号：US13696291
申请日：2011-05-05
申请人： Edward L. Chan , James Keller
发明人： Edward L. Chan , James Keller
IPC分类号： C07K16/00 , C12Q1/68 , C07K14/71 , G01N33/574 , C07K16/40 , C12N9/12 , G01N33/74
CPC分类号： C12Q1/6886 , C07K14/71 , C07K16/40 , C07K2319/00 , C07K2319/23 , C07K2319/42 , C07K2319/43 , C07K2319/60 , C12N9/12 , G01N33/57407 , G01N33/74 , G01N2333/71 , G01N2800/56
摘要： Described herein are truncated EGF receptor polypeptides, nucleic acids encoding them, and methods of using them to help select a method of treatment for an EGFR-related cancer, to predict clinical outcome, and to detect micrometastases or minimal residual disease. High EGFR expression and phosphorylated EGFR predicts poor survival in head and neck cancer patients, but does not correlate with advanced stage disease. In our studies, we determined that clinical biological correlates are likely to be more accurate when different aspects of EGFR are evaluated in combination. We analyzed EGFR phosphorylation, expression and mutations in 60 primary head and neck tumors. We not only found that head and neck tumors with either truncated or activated EGFR tend to have higher tumor and nodal stage, but also discovered three EGFR truncations.
摘要翻译：本文描述的是截短的EGF受体多肽，编码它们的核酸，以及使用它们帮助选择EGFR相关癌症的治疗方法，预测临床结果以及检测微转移或微小残留疾病的方法。高EGFR表达和磷酸化EGFR预测头颈癌患者的生存率差，但与晚期阶段疾病无关。在我们的研究中，我们确定临床生物相关性可以更准确地评估EGFR的不同方面。我们分析了60例原发性头颈部肿瘤中的EGFR磷酸化，表达和突变。我们不仅发现具有截短或活化的EGFR的头颈部肿瘤倾向于具有较高的肿瘤和淋巴结阶段，而且还发现三个EGFR截短。

9. 发明申请

US20120226542A1 PROVIDING COUPONS VIA A MOBILE DEVICE 审中-公开
标题翻译：通过移动设备提供优惠
公开(公告)号：US20120226542A1
公开(公告)日：2012-09-06
申请号：US13356566
申请日：2012-01-23
申请人： Nicholas Blosser , Greg Keene , James Keller , Raven Zachary , Jennifer Adams
发明人： Nicholas Blosser , Greg Keene , James Keller , Raven Zachary , Jennifer Adams
IPC分类号： G06Q30/02
CPC分类号： G06Q30/02
摘要： A facility for distributing electronic coupons is described. The facility presents to a user indications of each of at least one coupon pack. Each coupon pack comprises a plurality of independently-redeemable electronic coupons. The facility receives user input selecting an indicated coupon pack, and uses payment information associated with the user to collect a price indicated for the selected coupon pack. The facility then makes the selected coupon pack available for use by the user such that the user may redeem any of the electronic coupons of the selected coupon pack.
摘要翻译：描述了分发电子券的设施。该设施向用户呈现每个至少一个优惠券包的指示。每个优惠券包包括多个独立可兑换的电子优惠券。该设施接收用户输入选择所指示的优惠券包，并且使用与用户相关联的支付信息来收集针对所选优惠券组指示的价格。然后，该设施使所选择的优惠券包可供用户使用，使得用户可以兑换所选择的优惠券包的任何电子优惠券。

10. 发明申请

US20060180528A1 Waste water recovery system 有权
标题翻译：废水回收系统
公开(公告)号：US20060180528A1
公开(公告)日：2006-08-17
申请号：US11060112
申请日：2005-02-17
申请人： James Keller
发明人： James Keller
IPC分类号： B01D35/16
CPC分类号： B01D35/12 , B01D29/114 , B01D29/66 , Y10S15/02
摘要： A waste water recovery system to filter and recirculate waste water to a wash system including a fluid recovery line, a fluid supply line and a fluid backwash line comprising a filter assembly including a water filtering section to receive waste water from the wash system and to recirculate filtered water to the wash system and a filter backwash section to selectively clean the water filtering section when a system condition exists, and a fluid control including a plurality of valve assemblies operatively coupled between the wash system, the water filtering section and the filter backwash section to selectively control the circulation of water through the water filtering section to recirculate the recovery water to the wash system and to periodically clean the water filtering section.
摘要翻译：一种用于将废水过滤并再循环到洗涤系统的废水回收系统，所述洗涤系统包括流体回收管线，流体供应管线和流体反洗管线，其包括过滤器组件，所述过滤器组件包括用于从洗涤系统接收废水并再循环过滤水到洗涤系统和过滤器反冲洗部分，以在系统状态存在时选择性地清洁水过滤部分，以及包括多个阀组件的流体控制器，其可操作地联接在洗涤系统，水过滤部分和过滤器反冲洗部分以选择性地控制水通过水过滤部分的循环，以将回收水再循环到洗涤系统并周期性地清洁水过滤部分。

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