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1. 发明申请

WO2008115968A1 INTEGRATED CIRCUIT HAVING RECEIVER JITTER TOLERANCE ("JTOL") MEASUREMENT 审中-公开
标题翻译：具有接收机耐久度（“JTOL”）测量的集成电路
公开(公告)号：WO2008115968A1
公开(公告)日：2008-09-25
申请号：PCT/US2008/057455
申请日：2008-03-19
申请人： RAMBUS INCORPORATED , LEE, Hae-chang , KIM, Jaeha , LEIBOWITZ, Brian
发明人： LEE, Hae-chang , KIM, Jaeha , LEIBOWITZ, Brian
IPC分类号： G01R31/317
CPC分类号： G01R29/26 , G01R31/31709 , G01R31/31725
摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
摘要翻译：能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样。从接收器输出的采样数据值用于评估集成电路的抖动容限。

2. 发明申请

WO2009099595A1 RECEIVER WITH ENHANCED CLOCK AND DATA RECOVERY 审中-公开
标题翻译：接收器具有增强的时钟和数据恢复
公开(公告)号：WO2009099595A1
公开(公告)日：2009-08-13
申请号：PCT/US2009/000687
申请日：2009-01-30
申请人： RAMBUS, INC. , LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIM, Jaeha , SAVOJ, Jafar
发明人： LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIM, Jaeha , SAVOJ, Jafar
IPC分类号： H04L7/033 , H04L7/00 , H04L25/03 , H04L25/49
CPC分类号： H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
摘要： A receiver (102) device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
摘要翻译：接收机（102）设备利用基于边缘的时钟和数据恢复来实现增强的数据接收，例如使用闪存模数转换器架构。在示例实施例中，设备实现第一相位调节控制回路，例如，爆炸相位检测器，其通过调整边沿时钟的相位来检测数据转换，以利用边缘采样器在最优边缘时间调整采样的采样器。该循环可以通过调整诸如闪存ADC的数据采样器的数据时钟的相位来进一步调整接收数据间隔中的采样以实现最佳数据接收。该装置还可以实现具有例如波特率相位检测器的第二相位调整控制回路，波形率相位检测器检测数据间隔以便在数据采样器的最佳数据时间进一步调整采样。

3. 发明申请

WO2009075713A4 APPARATUS AND METHODS FOR DIFFERENTIAL SIGNAL RECEIVING 审中-公开
公开(公告)号：WO2009075713A4
公开(公告)日：2009-06-18
申请号：PCT/US2008/012322
申请日：2008-10-29
申请人： RAMBUS, INC. , LEIBOWITZ, Brian, S. , KIM, Jaeha , LEE, Hae-Chang
发明人： LEIBOWITZ, Brian, S. , KIM, Jaeha , LEE, Hae-Chang
IPC分类号： H04L7/033 , G06F13/42 , G11C7/10 , H03K5/13 , H04L7/00
摘要： A differential signal receiver 106 implements intra-pair skew compensation for improving data transfer on a differential channel. In an embodiment, the receiver implements sampling by- multiple clocks with different phases such that the signals of the differential channel may be separately or individually time adjusted to account for skew between them so that they may be differentially compared for data resolution. In one embodiment, a positive sampler and negative sampler are controlled by distinct clock signals to permit, at different times, sampling and holding of the positive and negative signals representing a data bit on the differential channel. A differential decision circuit may then differentially resolve the data using a latter one of the distinct clock signals. Timing generation circuitry for producing the offset clocks may include a skew detector that permits dynamic adjustment of the different clock signals according to skew associated with the signals of the differential channel.

4. 发明申请

WO2009058790A1 SIGNALING WITH SUPERIMPOSED DIFFERENTIAL-MODE AND COMMON-MODE SIGNALS 审中-公开
标题翻译：信号与超级差分模式和共模信号
公开(公告)号：WO2009058790A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/081478
申请日：2008-10-28
申请人： RAMBUS INC. , LIN, Qi , LEE, Hae-Chang , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
发明人： LIN, Qi , LEE, Hae-Chang , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
IPC分类号： H04L5/20
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/0262
摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,- the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
摘要翻译：数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。第一和第二相应的传输线包括数据接收器电路外部的一对传输线。第一和第二接口从一对传输线接收传输信号。共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。所提取的数据信号具有对应于所提取的时钟信号的频率的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。差分模式电路与提取的时钟信号同步。

5. 发明申请

WO2008144152A1 INJECTION-LOCKED CLOCK MULTIPLIER 审中-公开
标题翻译：注射锁定时间累加器
公开(公告)号：WO2008144152A1
公开(公告)日：2008-11-27
申请号：PCT/US2008/061118
申请日：2008-04-22
申请人： RAMBUS INC. , LEIBOWITZ, Brian S. , FRANS, Yohan , LEE, Hae-chang , KIM, Jaeha
发明人： FRANS, Yohan , LEE, Hae-chang , KIM, Jaeha
IPC分类号： H03L7/24
CPC分类号： H03L7/24 , H03L7/083 , H03L7/099 , H03L7/10
摘要： Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit. In addition, an injection circuit is coupled to the oscillator. This injection circuit provides a second clock signal having a second frequency to the oscillator. Note that the second clock signal injection locks a phase and/or the first frequency of the first clock signal. Also note that a ratio of the first frequency to the second frequency is greater than or equal to one.
摘要翻译：描述时钟电路的实施例。该时钟电路包括振荡器，其包括具有谐振频率的谐振电路，该谐振电路输出具有第一频率的第一时钟信号。此外，数字控制器耦合到振荡器。该数字控制器在时钟电路的第一操作模式期间修改振荡器的谐振频率，并且在时钟电路的第二操作模式期间中止修改。此外，注入电路耦合到振荡器。该注入电路向振荡器提供具有第二频率的第二时钟信号。注意，第二时钟信号注入锁定第一时钟信号的相位和/或第一频率。还要注意，第一频率与第二频率的比率大于或等于1。

6. 发明申请

WO2008118659A1 HARDWARE AND METHOD TO TEST PHASE LINEARITY OF PHASE SYNTHESIZER 审中-公开
标题翻译：用于测试相合成相的相位线性的硬件和方法
公开(公告)号：WO2008118659A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/056952
申请日：2008-03-14
申请人： RAMBUS INC. , KIM, Jaeha , LEE, Hae-chang , GREER, Thomas, H., III
发明人： KIM, Jaeha , LEE, Hae-chang , GREER, Thomas, H., III
IPC分类号： H03M1/10 , G01R31/317 , H03M1/66
CPC分类号： H03M1/109 , G01R31/31725 , G01R31/31726 , G01R31/31727 , H03M1/66
摘要： A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output.
摘要翻译：用于测试相位合成器的相位线性度的电路，其合成具有相应于输入到相位合成器的数字相位值的相位的输出时钟。数字计数器向相位合成器提供数字相位值。数字计数器接收与输入时钟同步的计数器时钟。数字相位值由数字计数器步进，从而移位输出时钟的频率。对相位合成器的相位线性度分析输出时钟，以产生相位线性分析输出。

7. 发明申请

WO2011106052A1 DECISION FEEDBACK EQUALIZER 审中-公开
标题翻译：决策反馈均衡器
公开(公告)号：WO2011106052A1
公开(公告)日：2011-09-01
申请号：PCT/US2010/058088
申请日：2010-11-24
申请人： RAMBUS INC. , LEIBOWITZ, Brian , KIM, Jaeha
发明人： LEIBOWITZ, Brian , KIM, Jaeha
IPC分类号： H04L27/01 , H03K7/02
CPC分类号： H04L25/03057 , H03M1/004 , H03M1/123 , H03M1/1245 , H03M1/362 , H04L25/03146 , H04L25/03885 , H04L2025/03363 , H04L2025/03369
摘要： A decision- feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.
摘要翻译：在相同符号时间内，判决反馈均衡器（DFE）对M个参考采样模拟输入信号以产生M个推测采样。在DFE中选择逻辑然后解码先前为先前符号时间分辨的N个比特，以选择M个推测样本之一作为当前分辨比特。然后将当前解析的位存储为最近以前解析的位，以准备下一个符号时间。选择逻辑可以是可编程的，以适应过程，环境和系统变化。

8. 发明申请

WO2009058789A1 SIGNALING WITH SUPERIMPOSED CLOCK AND DATA SIGNALS 审中-公开
标题翻译：用超级时钟和数据信号进行信号
公开(公告)号：WO2009058789A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/081477
申请日：2008-10-28
申请人： RAMBUS INC. , LIN, Qi , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
发明人： LIN, Qi , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
IPC分类号： H04L7/027 , H04L7/00
CPC分类号： H04L7/0008 , H04L7/065 , H04L25/0276 , H04L25/14
摘要： A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.
摘要翻译：数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。第一速率是第二速率的倍数，其中倍数大于1。数据传输电路还包括与符号时钟同步的数据驱动器。数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。数据信号和时钟信号同时被驱动到一个或多个传输线上。

9. 发明申请

WO2008150321A1 METHODS AND SYSTEMS FOR TRANSMITTING AUXILIARY DATA BY MODULATING PRE-EMPHASIS FILTER COEFFICIENTS 审中-公开
标题翻译：通过调整前置滤波器系数来传输辅助数据的方法和系统
公开(公告)号：WO2008150321A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/003961
申请日：2008-03-25
申请人： RAMBUS INC. , KIM, Jaeha , LEE, Haechang , CHUN, Jung-Hoon , ZERBE, Jared
发明人： KIM, Jaeha , LEE, Haechang , CHUN, Jung-Hoon , ZERBE, Jared
IPC分类号： H04L5/04 , H04L25/03
CPC分类号： H04L25/03343 , H04B1/126 , H04L5/04 , H04L2025/03356 , H04L2025/03477 , H04L2025/03802
摘要： A signaling system supports main and auxiliary communication channels between integrated circuits (105,110) in the same direction over a single link (115). An equalizing transmitter (117) applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel (115). The transmitter modulates (133) at least one of the filter coefficients (155) with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver (120) ignores the apparent ISI to recover the main data, while an auxiliary receiver (135) detects (170) and demodulates (172) the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread- spectrum techniques to reduce the impact of the auxiliary data on the main data.
摘要翻译：信号系统通过单个链路（115）在相同方向上支持集成电路（105,110）之间的主和辅助通信信道。当通过通信信道（115）发送主数据时，均衡发射机（117）应用适当的滤波器系数来最小化符号间干扰的影响。发射机利用辅助数据调制（133）至少一个滤波器系数（155）以在所发送的信号中引起明显的ISI。辅助接收机（135）检测（170）并解调（172）明显的ISI以恢复辅助数据，主接收机（120）忽略恢复主数据的明显ISI。可以使用扩频技术对辅助数据进行编码，以减少辅助数据对主数据的影响。

10. 发明申请

WO2009026513A4 CLOCK GENERATOR CIRCUITS WITH NON-VOLATILE MEMORY FOR STORING AND/OR FEEDBACK-CONTROLLING PHASE AND FREQUENCY 审中-公开
公开(公告)号：WO2009026513A4
公开(公告)日：2009-02-26
申请号：PCT/US2008/074008
申请日：2008-08-22
申请人： RAMBUS INC. , KIM, Jaeha , HAUKNESS, Brent
发明人： KIM, Jaeha , HAUKNESS, Brent
IPC分类号： H03L7/14 , H03L7/187 , H03L7/093
摘要： A clock-signal generator (e.g. a PLL or a DLL) uses non- volatile memory to store an analog control voltage that determines an output phase and/or frequency of the clock-signal generator. Locked loops take time to lock on a given reference frequency. To keep this time to a minimum, a non-volatile memory stores the control voltage during periods of inactivity, such as when the signal generator is powered down or in a standby mode. Non- volatile memory stores control voltages during operation in other embodiments to relax the area requirements otherwise required for integration capacitors to store phase and frequency information.

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