专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2009058790A1 SIGNALING WITH SUPERIMPOSED DIFFERENTIAL-MODE AND COMMON-MODE SIGNALS 审中-公开
标题翻译：信号与超级差分模式和共模信号
公开(公告)号：WO2009058790A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/081478
申请日：2008-10-28
申请人： RAMBUS INC. , LIN, Qi , LEE, Hae-Chang , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
发明人： LIN, Qi , LEE, Hae-Chang , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
IPC分类号： H04L5/20
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/0262
摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,- the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
摘要翻译：数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。第一和第二相应的传输线包括数据接收器电路外部的一对传输线。第一和第二接口从一对传输线接收传输信号。共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。所提取的数据信号具有对应于所提取的时钟信号的频率的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。差分模式电路与提取的时钟信号同步。

2. 发明申请

WO2009099595A1 RECEIVER WITH ENHANCED CLOCK AND DATA RECOVERY 审中-公开
标题翻译：接收器具有增强的时钟和数据恢复
公开(公告)号：WO2009099595A1
公开(公告)日：2009-08-13
申请号：PCT/US2009/000687
申请日：2009-01-30
申请人： RAMBUS, INC. , LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIM, Jaeha , SAVOJ, Jafar
发明人： LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIM, Jaeha , SAVOJ, Jafar
IPC分类号： H04L7/033 , H04L7/00 , H04L25/03 , H04L25/49
CPC分类号： H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
摘要： A receiver (102) device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
摘要翻译：接收机（102）设备利用基于边缘的时钟和数据恢复来实现增强的数据接收，例如使用闪存模数转换器架构。在示例实施例中，设备实现第一相位调节控制回路，例如，爆炸相位检测器，其通过调整边沿时钟的相位来检测数据转换，以利用边缘采样器在最优边缘时间调整采样的采样器。该循环可以通过调整诸如闪存ADC的数据采样器的数据时钟的相位来进一步调整接收数据间隔中的采样以实现最佳数据接收。该装置还可以实现具有例如波特率相位检测器的第二相位调整控制回路，波形率相位检测器检测数据间隔以便在数据采样器的最佳数据时间进一步调整采样。

3. 发明申请

WO2009075713A4 APPARATUS AND METHODS FOR DIFFERENTIAL SIGNAL RECEIVING 审中-公开
公开(公告)号：WO2009075713A4
公开(公告)日：2009-06-18
申请号：PCT/US2008/012322
申请日：2008-10-29
申请人： RAMBUS, INC. , LEIBOWITZ, Brian, S. , KIM, Jaeha , LEE, Hae-Chang
发明人： LEIBOWITZ, Brian, S. , KIM, Jaeha , LEE, Hae-Chang
IPC分类号： H04L7/033 , G06F13/42 , G11C7/10 , H03K5/13 , H04L7/00
摘要： A differential signal receiver 106 implements intra-pair skew compensation for improving data transfer on a differential channel. In an embodiment, the receiver implements sampling by- multiple clocks with different phases such that the signals of the differential channel may be separately or individually time adjusted to account for skew between them so that they may be differentially compared for data resolution. In one embodiment, a positive sampler and negative sampler are controlled by distinct clock signals to permit, at different times, sampling and holding of the positive and negative signals representing a data bit on the differential channel. A differential decision circuit may then differentially resolve the data using a latter one of the distinct clock signals. Timing generation circuitry for producing the offset clocks may include a skew detector that permits dynamic adjustment of the different clock signals according to skew associated with the signals of the differential channel.

4. 发明申请

WO2008076700A2 INTERFACE WITH VARIABLE DATA RATE 审中-公开
标题翻译：具有可变数据速率的接口
公开(公告)号：WO2008076700A2
公开(公告)日：2008-06-26
申请号：PCT/US2007/087027
申请日：2007-12-10
申请人： RAMBUS INC. , FRANS, Yohan, U. , LEE, Hae-Chang , LEIBOWITZ, Brian, S. , LI, Simon , NGUYEN, Nhat, M.
发明人： FRANS, Yohan, U. , LEE, Hae-Chang , LEIBOWITZ, Brian, S. , LI, Simon , NGUYEN, Nhat, M.
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
摘要： A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined errorrate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
摘要翻译：一种设备包括耦合到节点的发射器，其中节点将耦合到有线链路。发射机具有多种操作模式，包括校准模式，其中根据有线链路以预定的错误率对应的电压余量来确定有线链路上的通信数据速率的范围。通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。

5. 发明申请

WO2008063431A2 EDGE BASED PARTIAL RESPONSE EQUALIZATION 审中-公开
标题翻译：基于边缘部分响应均衡
公开(公告)号：WO2008063431A2
公开(公告)日：2008-05-29
申请号：PCT/US2007/023600
申请日：2007-11-09
申请人： RAMBUS, INC. , LEIBOWITZ, Brian, S. , LEE, Hae-Chang , REN, Jihong , RATNAYAKE, Ruwan
发明人： LEIBOWITZ, Brian, S. , LEE, Hae-Chang , REN, Jihong , RATNAYAKE, Ruwan
IPC分类号： H04L25/03 , H04L25/497
CPC分类号： H04L25/03057 , G06F13/38 , H04L25/03019 , H04L25/0307 , H04L2025/03369 , H04L2025/03617
摘要： A device (102) implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data signal (104). The tap weight adapter circuit (119) sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.
摘要翻译：设备（102）利用基于边缘的部分响应判决反馈均衡来实现数据接收。在一个示例性实施例中，该装置实现一个抽头权重适配器电路（114），其设置用于调整接收到的数据信号（104）的抽头权重。抽头重量适配器电路（119）基于先前确定的数据值设置抽头权重，并使用一组边缘采样器从接收数据信号的边缘分析输入。边缘分析（116）可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样数据信号。时钟发生电路（220）生成边沿时钟信号以控制由边缘采样器组执行的边缘采样。可以根据边缘采样器的信号和由均衡器确定的先前数据值来生成边沿时钟信号。

6. 发明申请

WO2008085964A3 ADAPTIVE CONTINUOUS-TIME LINE EQUALIZER FOR CORRECTING THE FIRST POST-CURSOR ISI 审中-公开
公开(公告)号：WO2008085964A3
公开(公告)日：2008-07-17
申请号：PCT/US2008/000249
申请日：2008-01-07
申请人： RAMBUS INC. , LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIZER, Jade, M. , GREER III, Thomas, H. , BANSAL, Akash
发明人： LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIZER, Jade, M. , GREER III, Thomas, H. , BANSAL, Akash
IPC分类号： H04L25/03
摘要： A receiver includes a continuous-time equalizer (120), a decision-feedback equalizer (DFE) (125), data and error sampling logic (130), and an adaptation engine (135). The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

7. 发明申请

WO2008070138A2 METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES 审中-公开
标题翻译：用于设备之间的通道均衡化的不对称分配的方法和电路
公开(公告)号：WO2008070138A2
公开(公告)日：2008-06-12
申请号：PCT/US2007/024948
申请日：2007-12-05
申请人： RAMBUS INC. , ZERBE, Jared, L. , ASSADERAGHI, Fariborz , LEIBOWITZ, Brian, S. , LEE, Hae-chang , REN, Jihong , LIN, Qi
发明人： ZERBE, Jared, L. , ASSADERAGHI, Fariborz , LEIBOWITZ, Brian, S. , LEE, Hae-chang , REN, Jihong , LIN, Qi
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
摘要翻译：收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

8. 发明申请

WO2008045167A1 CLOCK AND DATA RECOVERY EMPLOYING PIECE-WISE ESTIMATION OF THE DERIVATIVE OF THE FREQUENCY 审中-公开
标题翻译：时钟和数据恢复采用频率衍生的智能估计
公开(公告)号：WO2008045167A1
公开(公告)日：2008-04-17
申请号：PCT/US2007/019418
申请日：2007-09-05
申请人： RAMBUS, INC. , LEE, Hae-chang , GREER, Thomas, H., III , KIZER, Jade, M. , LEIBOWITZ, Brian, S. , HOROWITZ, Mark, A.
发明人： LEE, Hae-chang , GREER, Thomas, H., III , KIZER, Jade, M. , LEIBOWITZ, Brian, S. , HOROWITZ, Mark, A.
IPC分类号： H03L7/00
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.
摘要翻译：一种用于执行时钟数据恢复的系统和方法。系统根据数据发送器时钟的频率和接收机时钟15的频率之间的偏移的变化率的至少三个估计来设置恢复的时钟信号30的相位。

9. 发明申请

WO2009058789A1 SIGNALING WITH SUPERIMPOSED CLOCK AND DATA SIGNALS 审中-公开
标题翻译：用超级时钟和数据信号进行信号
公开(公告)号：WO2009058789A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/081477
申请日：2008-10-28
申请人： RAMBUS INC. , LIN, Qi , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
发明人： LIN, Qi , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
IPC分类号： H04L7/027 , H04L7/00
CPC分类号： H04L7/0008 , H04L7/065 , H04L25/0276 , H04L25/14
摘要： A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.
摘要翻译：数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。第一速率是第二速率的倍数，其中倍数大于1。数据传输电路还包括与符号时钟同步的数据驱动器。数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。数据信号和时钟信号同时被驱动到一个或多个传输线上。

10. 发明申请

WO2012021380A3 FAST-WAKE MEMORY 审中-公开
公开(公告)号：WO2012021380A3
公开(公告)日：2012-02-16
申请号：PCT/US2011/046669
申请日：2011-08-04
申请人： RAMBUS INC. , WARE, Frederick, A. , ZERBE, Jared, L. , LEIBOWITZ, Brian, S.
发明人： WARE, Frederick, A. , ZERBE, Jared, L. , LEIBOWITZ, Brian, S.
IPC分类号： G11C7/22 , G11C7/10 , G06F13/16 , G06F12/00
摘要： One or more timing signals used to time data and command transmission over highspeed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different- frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式