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1. 发明申请

WO2010080174A1 MESOCHRONOUS SIGNALING SYSTEM WITH CORE-CLOCK SYNCHRONIZATION 审中-公开
标题翻译：具有核心时钟同步的MESOCHRONOUS信号系统
公开(公告)号：WO2010080174A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050023
申请日：2009-07-09
申请人： RAMBUS INC. , WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G11C11/407 , H03K19/0175
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以使得能够以源同步定时参考不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

2. 发明申请

WO2010080173A1 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 审中-公开
标题翻译：具有时钟停止低功耗模式的MESOCHRONOUS信号系统
公开(公告)号：WO2010080173A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050020
申请日：2009-07-09
申请人： RAMBUS INC. , WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G06F1/04 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

3. 发明申请

WO2008100523A3 LOW-POWER CLOCK GENERATION AND DISTRIBUTION CIRCUITRY 审中-公开
公开(公告)号：WO2008100523A3
公开(公告)日：2008-08-21
申请号：PCT/US2008/001869
申请日：2008-02-12
申请人： RAMBUS INC. , POULTON, John, W. , PALMER, Robert, E. , FULLER, Andrew, M.
发明人： POULTON, John, W. , PALMER, Robert, E. , FULLER, Andrew, M.
IPC分类号： G06F1/10 , G06F1/32
摘要： A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.

4. 发明申请

WO2008100843A2 EDGE-BASED SAMPLER OFFSET CORRECTION 审中-公开
标题翻译：基于边缘采样器偏移校正
公开(公告)号：WO2008100843A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/053552
申请日：2008-02-11
申请人： RAMBUS INC. , FULLER, Andrew, M. , POULTON, John
发明人： FULLER, Andrew, M. , POULTON, John
IPC分类号： H04L25/06
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： A receiver circuit includes a first sampler and a second sampler. A clock-data-recovery circuit in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage of the given sampler in a timing region proximate to the signal crossing point in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.
摘要翻译：接收器电路包括第一采样器和第二采样器。接收机电路中的时钟数据恢复电路调整接收器电路的采样时间，使得采样时间接近与接收信号相关联的眼图的边缘处的信号交叉点。接收器电路中的偏移校准电路确定并调整给定采样器的偏移电压，其可以是第一采样器或第二采样器。该偏移校准电路可以在靠近信号交叉点的定时区域中确定给定采样器的当前偏移电压，其中时钟数据恢复电路基于当前偏移电压来抖动当前采样时间。此外，时钟数据恢复电路和偏移校准电路可以迭代地收敛于给定采样器的信号交叉点和剩余偏移电压。

5. 发明申请

WO2022039945A1 CIRCUITS AND METHODS FOR SELF-ADAPTIVE DECISION-FEEDBACK EQUALIZATION A MEMORY SYSTEM 审中-公开
公开(公告)号：WO2022039945A1
公开(公告)日：2022-02-24
申请号：PCT/US2021/044932
申请日：2021-08-06
申请人： RAMBUS INC.
发明人： FULLER, Andrew, M. , DALY, Barry, William , GIOVANNINI, Thomas, J. , LUO, Lei , HOSSAIN, Masum
IPC分类号： G11C7/10
摘要： Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer in a set has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a timing- reference signal (e.g. a clock or strobe) that is common to the set. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.

6. 发明公开

EP3258386A1 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 有权转让
标题翻译：具有时钟停止低功耗模式的中间信令系统
公开(公告)号：EP3258386A1
公开(公告)日：2017-12-20
申请号：EP17174681.1
申请日：2009-07-09
申请人： Rambus Inc.
发明人： WARE, Frederick, A , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G06F13/16 , G06F3/06 , G06F1/12 , G11C7/10 , G11C7/22 , G11C7/04 , G06F1/32 , G11C11/4076 , G11C11/4096 , G06F13/36 , G06F12/0855 , G06F9/38
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable highspeed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信令系统中，集成电路设备包括开环时钟分配电路和发送电路，其协作以实现源同步定时参考不伴随的信息承载符号的高速传输。响应于外部提供的时钟信号，开环时钟分配电路产生发送时钟信号，并且响应于发送时钟信号的转变，发送电路将符号序列输出到外部信号线上。每个符号在发送电路的输出端对于符号时间是有效的，并且发送时钟信号和外部提供的时钟信号之间的相位偏移被允许漂移至少符号时间。

7. 发明公开

EP2353058A1 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 有权转让
标题翻译： MESOCHRONES SIGNALISIERUNGSSYSTEM MIT TAKTGESTEUERTEM NIEDRIGLEISTUNGSMODUS
公开(公告)号：EP2353058A1
公开(公告)日：2011-08-10
申请号：EP09837752.6
申请日：2009-07-09
申请人： Rambus Inc.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G06F1/04 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable highspeed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：集成电路存储器控制器向存储器件输出处于第一状态的第一信号，以使存储器件内的同步数据发送和接收电路能够操作。存储器控制器内的事务队列存储要被服务的存储器读和写请求，分别要求存储器件内的同步数据发送和接收电路的操作。存储器控制器内的电源控制电路确定事务队列已经达到预定状态，并且作为响应，在第二状态下将第一信号输出到存储器件，以禁止存储器件内的同步数据发送和接收电路的操作。

8. 发明授权

EP3258386B1 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 有权转让
公开(公告)号：EP3258386B1
公开(公告)日：2019-05-01
申请号：EP17174681.1
申请日：2009-07-09
申请人： Rambus Inc.
发明人： WARE, Frederick, A , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G06F13/16 , G06F3/06 , G06F1/12 , G11C7/10 , G11C7/22 , G11C7/04 , G06F1/32 , G11C11/4076 , G11C11/4096 , G06F13/36 , G06F12/0855 , G06F9/38

9. 发明授权

EP2353058B1 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 有权转让
标题翻译：具有时钟停止低功耗模式的中间信令系统
公开(公告)号：EP2353058B1
公开(公告)日：2017-06-14
申请号：EP09837752.6
申请日：2009-07-09
申请人： Rambus Inc.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G06F1/04 , G06F1/32 , G06F12/00 , G06F13/16 , G11C7/04 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4096 , G06F13/36
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable highspeed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信令系统中，集成电路设备包括开环时钟分配电路和发送电路，它们协作以实现源同步定时基准不伴随的信息承载符号的高速传输。响应于外部提供的时钟信号，开环时钟分配电路产生发送时钟信号，并且响应于发送时钟信号的转变，发送电路将符号序列输出到外部信号线上。每个符号在发送电路的输出端对于符号时间是有效的，并且发送时钟信号和外部提供的时钟信号之间的相位偏移被允许漂移至少符号时间。

10. 发明公开

EP4200849A1 CIRCUITS AND METHODS FOR SELF-ADAPTIVE DECISION-FEEDBACK EQUALIZATION A MEMORY SYSTEM 审中-实审
公开(公告)号：EP4200849A1
公开(公告)日：2023-06-28
申请号：EP21858815.0
申请日：2021-08-06
申请人： Rambus Inc.
发明人： FULLER, Andrew, M. , DALY, Barry, William , GIOVANNINI, Thomas, J. , LUO, Lei , HOSSAIN, Masum
IPC分类号： G11C7/10

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