专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2017019495A1 BURST-TOLERANT DECISION FEEDBACK EQUALIZATION 审中-公开
标题翻译：稳定的决策反馈均衡
公开(公告)号：WO2017019495A1
公开(公告)日：2017-02-02
申请号：PCT/US2016/043534
申请日：2016-07-22
申请人： RAMBUS INC.
发明人： GIOVANNINI, Thomas, J. , ABHYANKAR, Abhijit
IPC分类号： H03H7/30
CPC分类号： H04L25/03878 , H04L25/03146
摘要： A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.
摘要翻译：第一序列的数据比特在第一比特时间间隔序列期间被移入信号接收机的存储元件，并且存储器访问命令指示在第二序列期间在信号接收器内接收第二数据比特序列的位时间间隔。取决于在第一和第二比特时间间隔之间是否会发生一个或多个比特时间间隔，移位寄存器存储元件的内容被有条件地用预定的种子比特组重写。至少部分地基于移位寄存器存储元件的内容生成的均衡信号用于调整代表第二数据位序列的一个或多个位的各个信号电平。

2. 发明申请

WO2016089563A1 HIGH PERFORMANCE, HIGH CAPACITY MEMORY SYSTEMS AND MODULES 审中-公开
标题翻译：高性能，高容量存储系统和模块
公开(公告)号：WO2016089563A1
公开(公告)日：2016-06-09
申请号：PCT/US2015/060057
申请日：2015-11-11
申请人： RAMBUS INC.
发明人： WARE, Frederick, A. , TSERN, Ely , LINSTADT, John, Eric , GIOVANNINI, Thomas, J. , HAMPEL, Craig, E. , BEST, Scott, C. , YAN, John
IPC分类号： G06F13/16 , G11C7/10
CPC分类号： G06F13/1678 , G06F13/1673 , G06F13/1694
摘要： Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility, or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.
摘要翻译：描述的是具有内存模块插槽的主板，它们接受传统内存模块以实现向后兼容，或接受更多数量的可配置模块以支持增加的内存容量。可配置模块可以与传统主板向后兼容。配有可配置模块，主板支持高信令速率和容量的内存系统。

3. 发明申请

WO2022039945A1 CIRCUITS AND METHODS FOR SELF-ADAPTIVE DECISION-FEEDBACK EQUALIZATION A MEMORY SYSTEM 审中-公开
公开(公告)号：WO2022039945A1
公开(公告)日：2022-02-24
申请号：PCT/US2021/044932
申请日：2021-08-06
申请人： RAMBUS INC.
发明人： FULLER, Andrew, M. , DALY, Barry, William , GIOVANNINI, Thomas, J. , LUO, Lei , HOSSAIN, Masum
IPC分类号： G11C7/10
摘要： Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer in a set has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a timing- reference signal (e.g. a clock or strobe) that is common to the set. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.

4. 发明申请

WO2012145117A2 MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES 审中-公开
标题翻译：存储器组件和控制器，用于校准多个同步时序参考
公开(公告)号：WO2012145117A2
公开(公告)日：2012-10-26
申请号：PCT/US2012/029893
申请日：2012-03-21
申请人： RAMBUS INC. , GIOVANNINI, Thomas, J. , BEST, Scott, C. , LUO, Lei , SHAEFFER, Ian
发明人： GIOVANNINI, Thomas, J. , BEST, Scott, C. , LUO, Lei , SHAEFFER, Ian
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/227 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C29/56
摘要： A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.
摘要翻译：第一定时参考信号和第二定时参考信号被发送到存储器件。第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。从存储装置接收多个串行数据模式。第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。时间指示器均使用单个采样器进行测量。基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

5. 发明公开

EP4200849A1 CIRCUITS AND METHODS FOR SELF-ADAPTIVE DECISION-FEEDBACK EQUALIZATION A MEMORY SYSTEM 审中-实审
公开(公告)号：EP4200849A1
公开(公告)日：2023-06-28
申请号：EP21858815.0
申请日：2021-08-06
申请人： Rambus Inc.
发明人： FULLER, Andrew, M. , DALY, Barry, William , GIOVANNINI, Thomas, J. , LUO, Lei , HOSSAIN, Masum
IPC分类号： G11C7/10

6. 发明公开

EP3329593A1 BURST-TOLERANT DECISION FEEDBACK EQUALIZATION 有权转让
公开(公告)号：EP3329593A1
公开(公告)日：2018-06-06
申请号：EP16831119.9
申请日：2016-07-22
申请人： Rambus Inc.
发明人： GIOVANNINI, Thomas, J. , ABHYANKAR, Abhijit
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , G06F3/0604 , G06F3/0644 , G06F3/0673 , G11C19/00 , H04L25/03146 , H04L25/03878
摘要： A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式