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1. 发明专利

CA571050A MILK CARTON CRUSHER 未知
公开(公告)号：CA571050A
公开(公告)日：1959-02-24
申请号：CA571050D
申请人： PALMER ROBERT E
发明人： PALMER ROBERT E

2. 发明申请

WO2010080172A1 CLOCK-FORWARDING LOW-POWER SIGNALING SYSTEM 审中-公开
标题翻译：时钟转换低功率信号系统
公开(公告)号：WO2010080172A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050016
申请日：2009-07-09
申请人： RAMBUS INC. , WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W.
IPC分类号： G11C7/22 , G11C8/00 , G11C5/14
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以使得能够以源同步定时参考不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

3. 发明申请

WO2010080173A1 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 审中-公开
标题翻译：具有时钟停止低功耗模式的MESOCHRONOUS信号系统
公开(公告)号：WO2010080173A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050020
申请日：2009-07-09
申请人： RAMBUS INC. , WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G06F1/04 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

4. 发明申请

WO2008100494A4 DIFFERENTIAL RECEIVER WITH COMMON-GATE INPUT STAGE 审中-公开
标题翻译：差分接收器与通用输入级
公开(公告)号：WO2008100494A4
公开(公告)日：2009-02-12
申请号：PCT/US2008001826
申请日：2008-02-11
申请人： RAMBUS INC , PALMER ROBERT E , POULTON JOHN W
发明人： PALMER ROBERT E , POULTON JOHN W
IPC分类号： H04L25/02 , H03F3/45
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： A low-voltage differential communication system includes a low- and programmable-swing voltage-mode transmitter that delivers a low- voltage differential signal to a receiver via differential channel. The receiver employs two input transistors, each in a common-gate configuration, to recover the low- voltage differential signal. A current source in the receiver biases the input transistors such that their source voltages are nominally biased at the common- mode voltage of the differential signal, and their gate-source voltages remain essentially constant with common-mode-voltage fluctuations.
摘要翻译：低压差分通信系统包括一个低和可编程摆幅电压模式发送器，通过差分通道向接收器传送低电压差分信号。接收机采用两个输入晶体管，每个输入晶体管以共栅极配置，以恢复低电压差分信号。接收器中的电流源偏置输入晶体管，使得它们的源极电压在标称偏置在差分信号的共模电压上，并且它们的栅源电压在共模电压波动下保持基本恒定。

5. 发明申请

WO2008100523A3 LOW-POWER CLOCK GENERATION AND DISTRIBUTION CIRCUITRY 审中-公开
公开(公告)号：WO2008100523A3
公开(公告)日：2008-08-21
申请号：PCT/US2008/001869
申请日：2008-02-12
申请人： RAMBUS INC. , POULTON, John, W. , PALMER, Robert, E. , FULLER, Andrew, M.
发明人： POULTON, John, W. , PALMER, Robert, E. , FULLER, Andrew, M.
IPC分类号： G06F1/10 , G06F1/32
摘要： A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.

6. 发明申请

WO2008100494A2 HIGH-SPEED LOW-POWER DIFFERENTIAL RECEIVER 审中-公开
标题翻译：高速低功耗差分接收器
公开(公告)号：WO2008100494A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/001826
申请日：2008-02-11
申请人： RAMBUS INC. , PALMER, Robert, E. , POULTON, John, W.
发明人： PALMER, Robert, E. , POULTON, John, W.
IPC分类号： H04L25/02
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： A low-voltage differential communication system includes a low- and programmable-swing voltage-mode transmitter that delivers a low- voltage differential signal to a receiver via differential channel. The receiver employs two input transistors, each in a common-gate configuration, to recover the low- voltage differential signal. A current source in the receiver biases the input transistors such that their source voltages are nominally biased at the common- mode voltage of the differential signal, and their gate-source voltages remain essentially constant with common-mode-voltage fluctuations.
摘要翻译：低压差分通信系统包括一个低和可编程摆幅电压模式发送器，通过差分通道向接收器传送低电压差分信号。接收机采用两个输入晶体管，每个输入晶体管以共栅极配置，以恢复低电压差分信号。接收器中的电流源偏置输入晶体管，使得它们的源极电压在标称偏置在差分信号的共模电压上，并且它们的栅源电压在共模电压波动下保持基本恒定。

7. 发明申请

WO2006066167A1 LOW-POWER RECEIVER EQUALIZATION IN A CLOCKED SENSE AMPLIFIER 审中-公开
标题翻译：低功率接收器在时钟感测放大器中的均衡
公开(公告)号：WO2006066167A1
公开(公告)日：2006-06-22
申请号：PCT/US2005/045852
申请日：2005-12-14
申请人： RAMBUS , PALMER, Robert, E.
发明人： PALMER, Robert, E.
IPC分类号： H04L25/03 , H04L7/02 , H04B7/005 , G11C7/06 , G11C11/4091
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087 , H03F3/45183 , H03F2203/45544 , H04L25/03019
摘要： A receiver includes clocked, differential equalization circuitry to compensate for signal attenuation that varies with the frequency of the input signal received over a respective communication channel. The incoming signal is split into filtered and unfiltered signal components. Separate current-steering transistors coupled in parallel amplify the filtered and unfiltered components and sum the results. The filter or filters used to separate the signal components may be tunable, e.g. using voltage-controlled filter components. The ratio of device sizes for the current-steering transistors sets the magnitude of the boost applied to highfrequency components. The embodiments include adjustable or programmable current-steering networks to facilitate adjustments that accommodate the unique characteristics of individual communication channels.
摘要翻译：接收机包括时钟差分均衡电路，以补偿随着在相应通信信道上接收的输入信号的频率而变化的信号衰减。输入信号被分成已滤波和未滤波的信号分量。并联耦合的独立电流转向晶体管放大滤波和未滤波的元件并对结果求和。用于分离信号分量的滤波器或滤波器可以是可调谐的，例如，使用压控滤波器组件。电流转向晶体管的器件尺寸比设定了施加于高频元件的升压幅度。这些实施例包括可调或可编程的电流导向网络，以便于适应各个通信信道的独特特征的调整。

8. 发明申请

WO2010085405A1 MAINTENANCE OPERATIONS IN A DRAM 审中-公开
标题翻译： DRAM中的维护操作
公开(公告)号：WO2010085405A1
公开(公告)日：2010-07-29
申请号：PCT/US2010/020934
申请日：2010-01-13
申请人： RAMBUS INC. , WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W.
IPC分类号： G06F13/16 , G11C11/406
CPC分类号： G06F3/0619 , G06F3/0629 , G06F3/0659 , G06F3/0673 , G06F13/1636 , G06F13/1689 , G06Q10/00 , G06Q20/00 , G11C7/02 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C2211/4061
摘要： A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.
摘要翻译：一种系统包括存储器控制器和具有命令接口和多个存储器组的存储器件，每个存储体具有多行存储器单元。存储器控制器向存储器件发送自动刷新命令。响应于自动刷新命令，在第一时间间隔期间，存储器件执行刷新操作以刷新存储器单元，并且存储器件的命令接口在第一时间间隔的持续时间内被置于校准模式。同时，在第一时间间隔的至少一部分期间，存储器控制器执行存储器件的命令接口的校准。自动刷新命令可以指定要刷新存储器件的存储体的顺序，使得存储器件以指定的存储体顺序顺序刷新多个存储体中的相应行。

9. 发明申请

WO2010080176A1 MESOCHRONOUS SIGNALING SYSTEM WITH MULTIPLE POWER MODES 审中-公开
标题翻译：具有多种功率模式的MESOCHRONOUS信号系统
公开(公告)号：WO2010080176A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050044
申请日：2009-07-09
申请人： RAMBUS INC. , WARE, Frederick, A. , POULTON, John, W. , PALMER, Robert, E.
发明人： WARE, Frederick, A. , POULTON, John, W. , PALMER, Robert, E.
IPC分类号： G11C11/407 , G11C8/00 , H03L7/081
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以使得能够以源同步定时参考不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

10. 发明申请

WO2010080175A1 SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATION 审中-公开
标题翻译：具有非对称管理时序校准的信号系统
公开(公告)号：WO2010080175A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050039
申请日：2009-07-09
申请人： RAMBUS INC. , POULTON, John, W. , PALMER, Robert, E.
发明人： POULTON, John, W. , PALMER, Robert, E.
IPC分类号： G11C7/22 , G11C11/413
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

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