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1. 发明申请

WO2009065050A1 DATA-DEPENDET VOLTAGE REGULATOR 审中-公开
标题翻译：数据依赖电压调节器
公开(公告)号：WO2009065050A1
公开(公告)日：2009-05-22
申请号：PCT/US2008/083655
申请日：2008-11-14
申请人： RAMBUS INC. , FRANS, Yohan , LEIBOWITZ, Brian , NGUYEN, Nhat
发明人： FRANS, Yohan , LEIBOWITZ, Brian , NGUYEN, Nhat
IPC分类号： G05F1/56
CPC分类号： G05F1/56
摘要： A data-dependent voltage regulator maintains a relatively stable voltage in the presence of data-induced supply-current fluctuations. The regulator includes a feedback path through a replica load that provides a data-dependent replica voltage for fast feedback. The regulator reduces data-dependent supply- voltage fluctuations on a regulated voltage without resorting to a compensation current.
摘要翻译：数据相关的电压调节器在数据引起的电源电流波动的情况下保持相对稳定的电压。调节器包括通过复制负载的反馈路径，其提供用于快速反馈的数据相关副本电压。调节器可减少稳压电压下的数据相关电源电压波动，而无需使用补偿电流。

2. 发明申请

WO2011008356A2 TECHNIQUES FOR ADJUSTING CLOCK SIGNALS TO COMPENSATE FOR NOISE 审中-公开
标题翻译：调整时钟信号以补偿噪音的技术
公开(公告)号：WO2011008356A2
公开(公告)日：2011-01-20
申请号：PCT/US2010/036792
申请日：2010-05-31
申请人： RAMBUS INC. , ZERBE, Jared , BATRA, Pradeep , LEIBOWITZ, Brian
发明人： ZERBE, Jared , BATRA, Pradeep , LEIBOWITZ, Brian
IPC分类号： H03K19/0175 , H04L25/02 , H03K5/1252
CPC分类号： H04L25/0264 , G06F1/10 , H03K5/1252
摘要： A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.
摘要翻译：第一集成电路（IC）具有可调延迟电路和第一接口电路。向可调延迟电路提供第一时钟信号以产生提供给第一接口电路的延迟的时钟信号。第二IC具有电源电压检测电路和与第一IC传输数据的第二接口电路。电源电压检测电路向第一IC提供指示第二IC的电源电压中的噪声的噪声信号。可调节延迟电路根据噪声信号调整延迟的时钟信号的延迟。在其他实施例中，边缘彩色时钟信号通过使IC间的共同的高频抖动来减少集成电路（IC）之间的数据传输中的高频抖动的影响。在其他实施例中，电源电压用于在多个IC上产生时钟信号。

3. 发明申请

WO2013137863A1 CLOCK AND DATA RECOVERY HAVING SHARED CLOCK GENERATOR 审中-公开
标题翻译：具有共享时钟发生器的时钟和数据恢复
公开(公告)号：WO2013137863A1
公开(公告)日：2013-09-19
申请号：PCT/US2012/028912
申请日：2012-03-13
申请人： RAMBUS INC. , HOSSAIN, Masum , LEIBOWITZ, Brian , REN, Jihong
发明人： HOSSAIN, Masum , LEIBOWITZ, Brian , REN, Jihong
IPC分类号： H03L7/085 , H04L7/033
CPC分类号： H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
摘要： This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current- controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
摘要翻译：本公开提供了一种用于多车道通信系统的时钟恢复电路。使用相应的本地CDR电路从输入信号恢复本地时钟，并且相关联的CDR错误信号被聚合或以其他方式组合。作为来自多个接收机的误差信号的组合的函数的可控振荡频率产生由本地CDR电路共享使用的全局恢复时钟。电压或电流控制延迟线也可用于相位调整全局恢复时钟，以减轻带限制，通道相关的高频抖动。

4. 发明申请

WO2008085299A1 RECEIVER WITH CLOCK RECOVERY CIRCUIT AND ADAPTIVE SAMPLE AND EQUALIZER TIMING 审中-公开
标题翻译：采用时钟恢复电路和自适应采样和均衡时序
公开(公告)号：WO2008085299A1
公开(公告)日：2008-07-17
申请号：PCT/US2007/025634
申请日：2007-12-13
申请人： RAMBUS INC. , LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
发明人： LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
IPC分类号： H04L7/02 , H04L7/00 , H04L25/03
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter- symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
摘要翻译：接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。采样和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。

5. 发明申请

WO2011106052A1 DECISION FEEDBACK EQUALIZER 审中-公开
标题翻译：决策反馈均衡器
公开(公告)号：WO2011106052A1
公开(公告)日：2011-09-01
申请号：PCT/US2010/058088
申请日：2010-11-24
申请人： RAMBUS INC. , LEIBOWITZ, Brian , KIM, Jaeha
发明人： LEIBOWITZ, Brian , KIM, Jaeha
IPC分类号： H04L27/01 , H03K7/02
CPC分类号： H04L25/03057 , H03M1/004 , H03M1/123 , H03M1/1245 , H03M1/362 , H04L25/03146 , H04L25/03885 , H04L2025/03363 , H04L2025/03369
摘要： A decision- feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.
摘要翻译：在相同符号时间内，判决反馈均衡器（DFE）对M个参考采样模拟输入信号以产生M个推测采样。在DFE中选择逻辑然后解码先前为先前符号时间分辨的N个比特，以选择M个推测样本之一作为当前分辨比特。然后将当前解析的位存储为最近以前解析的位，以准备下一个符号时间。选择逻辑可以是可编程的，以适应过程，环境和系统变化。

6. 发明申请

WO2011059842A2 TECHNIQUES FOR PHASE DETECTION 审中-公开
标题翻译：相位检测技术
公开(公告)号：WO2011059842A2
公开(公告)日：2011-05-19
申请号：PCT/US2010/054900
申请日：2010-10-31
申请人： RAMBUS INC. , LEIBOWITZ, Brian , LEE, Hae-Chang , ARYANFAR, Farshid , CHANG, Kun-Yung , SHEN, Jie
发明人： LEIBOWITZ, Brian , LEE, Hae-Chang , ARYANFAR, Farshid , CHANG, Kun-Yung , SHEN, Jie
CPC分类号： H03D13/00 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/085
摘要： A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.
摘要翻译：相位检测电路可以包括两个相位检测器，每个相位检测器响应于输入信号的相位对齐而生成非零输出。输入信号基于两个周期性信号。当周期信号同相时，相位检测电路从另一相位检测器的输出信号中减去一个相位检测器的输出信号，以产生具有零值的信号。或者，相位检测器产生指示周期性信号之间的相位差的相位比较信号。响应于相位检测器的输入信号被同相对准，相位比较信号具有非零值。输入信号基于周期性信号。输出电路接收相位比较信号并且响应于周期性信号的相位对准而产生具有零值的输出。

7. 发明申请

WO2008115968A1 INTEGRATED CIRCUIT HAVING RECEIVER JITTER TOLERANCE ("JTOL") MEASUREMENT 审中-公开
标题翻译：具有接收机耐久度（“JTOL”）测量的集成电路
公开(公告)号：WO2008115968A1
公开(公告)日：2008-09-25
申请号：PCT/US2008/057455
申请日：2008-03-19
申请人： RAMBUS INCORPORATED , LEE, Hae-chang , KIM, Jaeha , LEIBOWITZ, Brian
发明人： LEE, Hae-chang , KIM, Jaeha , LEIBOWITZ, Brian
IPC分类号： G01R31/317
CPC分类号： G01R29/26 , G01R31/31709 , G01R31/31725
摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
摘要翻译：能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样。从接收器输出的采样数据值用于评估集成电路的抖动容限。

8. 发明申请

WO2020163187A1 METHOD OF PREVENTING OR TREATING TREATMENT-INDUCED GASTROINTESTINAL INJURY 审中-公开
公开(公告)号：WO2020163187A1
公开(公告)日：2020-08-13
申请号：PCT/US2020/016302
申请日：2020-02-03
申请人： YU, Jian , ZHANG, Lin , LEIBOWITZ, Brian
发明人： YU, Jian , ZHANG, Lin , LEIBOWITZ, Brian
IPC分类号： A61K31/045 , A61K31/496 , A61P1/00 , A61P39/02
摘要： Provided herein are compositions and methods for preventing or treating gastrointestinal injury induced by chemotherapy or radiotherapy.

9. 发明公开

EP2774151A1 DATA TRANSMISSION USING DELAYED TIMING SIGNALS 有权转让
标题翻译：与延迟时钟信号的通信
公开(公告)号：EP2774151A1
公开(公告)日：2014-09-10
申请号：EP12845819.7
申请日：2012-10-26
申请人： Rambus Inc.
发明人： WARE, Frederick A. , TSERN, Ely , LEIBOWITZ, Brian , ZERBE, Jared
IPC分类号： G11C7/00
CPC分类号： H03K5/13 , G06F13/00 , G06F13/1689 , G06F13/4243 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C29/022 , G11C29/023 , G11C29/028
摘要： An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

10. 发明授权

EP2115929B1 RECEIVER WITH CLOCK RECOVERY CIRCUIT AND ADAPTIVE SAMPLE AND EQUALIZER TIMING 有权转让
标题翻译： EMPFÄNGERMIT EINER TAKTWIEDERGEWINNUNGSSCHALTUNG UND ADAPTIVEM SAMPLE- UND ENTZERRERTIMING
公开(公告)号：EP2115929B1
公开(公告)日：2014-05-21
申请号：EP07853389.0
申请日：2007-12-13
申请人： Rambus Inc.
发明人： LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
IPC分类号： H04L7/02 , H04L7/00 , H04L25/03 , H04L7/033
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
摘要翻译：接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。样本和均衡器定时被转移到相对于当前符号具有较少的残余符号间干扰（ISI）能量的位置。可以使用信号质量的测量（诸如接收机误码率或滤波器抽头值的比较）来计算移位位置，以优化数据恢复的定时。

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