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1. 发明申请

WO2004001574A1 METHOD AND APPARATUS FOR THE DYNAMIC SCHEDULING OF DEVICE COMMANDS 审中-公开
标题翻译：用于设备命令动态调度的方法和装置
公开(公告)号：WO2004001574A1
公开(公告)日：2003-12-31
申请号：PCT/US2003/019802
申请日：2003-06-20
申请人： RAMBUS INC.
发明人： PEREGO, Richard, E. , WARE, Frederick, A. , HAMPEL, Craig, E. , TSERN, Ely, K.
IPC分类号： G06F3/00
CPC分类号： G06F13/1605
摘要： Methods and apparatuses for scheduling commands are described. According to various embodiments of the invention ,delay information (108, 112), is issued with an associated command (101, 103). The delay information (201, 206) directs the device for which the command is intended to either execute the command immediately or to delay the command for some period of time before execution. Multiple commands (207) can be queued for execution within the device (202, 203, 204).
摘要翻译：描述用于调度命令的方法和装置。根据本发明的各种实施例，发出具有相关命令（101,103）的延迟信息（108,112）。所述延迟信息（201,206）指示所述命令旨在的设备或者立即执行该命令，或者在执行之前延迟该命令一段时间。多个命令（207）可以排队等待在设备（202,203,204）内执行。

2. 发明申请

WO2005072299A2 PERIODIC CALIBRATION FOR COMMUNICATION CHANNELS BY DRIFT TRACKING 审中-公开
标题翻译：通过跟踪进行通信通道的定期校准
公开(公告)号：WO2005072299A2
公开(公告)日：2005-08-11
申请号：PCT/US2005/002139
申请日：2005-01-25
申请人： RAMBUS, INC. , HAMPEL, Craig, E. , WARE, Frederick, A. , PEREGO, Richard, E.
发明人： HAMPEL, Craig, E. , WARE, Frederick, A. , PEREGO, Richard, E.
IPC分类号： H04B1/38 , H04L7/00 , H04L7/04 , H04L7/10 , H04L27/00
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2 N -1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
摘要翻译：一种提供执行第一校准序列的方法和系统，例如在系统初始化时建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量在参数中漂移，并根据测量的漂移更新操作值。与第一校准序列相比，第二校准序列使用较少的通信信道资源。在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2 N比特的伪随机比特序列，其中N等于大于等于7，而第二校准序列使用短校准模式，例如小于16字节的固定码，例如短至2字节长。

3. 发明申请

WO2002071407A3 ASYNCHRONOUS, HIGH-BANDWIDTH MEMORY COMPONENT USING CALIBRATED TIMING ELEMENTS 审中-公开
公开(公告)号：WO2002071407A3
公开(公告)日：2002-09-12
申请号：PCT/US2002/002597
申请日：2002-01-30
申请人： RAMBUS, INC.
发明人： WARE, Frederick, A. , TSERN, Ely, K. , HAMPEL, Craig, E. , STARK, Donald, C.
IPC分类号： G11C7/10
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different synchronous delays and to strobe sequential pipeline elements of the memory device.

4. 发明申请

WO2022119704A2 DYNAMICALLY CONFIGURABLE MEMORY ERROR CONTROL SCHEMES 审中-公开
公开(公告)号：WO2022119704A2
公开(公告)日：2022-06-09
申请号：PCT/US2021/059492
申请日：2021-11-16
申请人： RAMBUS INC.
发明人： HAMPEL, Craig, E. , LINSTADT, John, Eric
IPC分类号： G06F11/08 , G06F11/14
摘要： A multi-host processing system may access memory devices (e.g., memory modules, memory integrated circuits, etc.) via memory nodes having memory controllers. The memory controllers may be configured to use more than one error control scheme when accessing the same memory devices. The selection of the error control scheme may be made based on the interface receiving the memory transaction request. The selection of the error control scheme may be made based on information in the memory transaction request. The selection of the error control scheme may be made based on the fabric physical address and a lookup table or address range registers. The selection of the error control scheme may be made based on the memory device physical address and a lookup table or address range registers.

5. 发明申请

WO2015113046A1 IMPLEMENTING ACCESS CONTROL BY SYSTEM-ON-CHIP 审中-公开
标题翻译：通过系统芯片实现访问控制
公开(公告)号：WO2015113046A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/013095
申请日：2015-01-27
申请人： RAMBUS INC.
发明人： HAMPEL, Craig, E. , CIORANESCO, Jean-Michel , PORTELLA DO CANTO, Rodrigo , OZARI DE ALMEIDA, Guilherme
IPC分类号： G06F21/44
CPC分类号： G06F21/6218 , G06F21/44 , G06F21/57 , G06F21/755 , G06F21/85 , H04L63/0227 , H04L63/06 , H04L63/08 , H04L63/0876 , H04L63/101 , H04L63/123
摘要： Systems and methods for implementing access control by systems-on-chip (SoCs). An example SoC may comprise: an access control unit comprising a secure memory for storing access control data, the access control unit to: receive a message comprising an access control data item; store the access control data item in the secure memory; perform at least one of: authenticating the message using a message digest function, or validating contents of the secure memory by comparing a stored reference value with a calculated value of a message digest function of the contents of the secure memory; and control, in view of the access control data item, access by an initiator device to a target device.
摘要翻译：通过片上系统（SoC）实现访问控制的系统和方法。示例SoC可以包括：访问控制单元，包括用于存储访问控制数据的安全存储器，所述访问控制单元用于：接收包括访问控制数据项的消息; 将访问控制数据项存储在安全存储器中; 执行以下至少之一：使用消息摘要功能认证所述消息，或者通过将所存储的参考值与所述安全存储器的内容的消息摘要功能的计算值进行比较来验证所述安全存储器的内容; 并且鉴于访问控制数据项，控制启动器设备到目标设备的访问。

6. 发明申请

WO2009137157A1 INDEPENDENT THREADING OF MEMORY DEVICES DISPOSED ON MEMORY MODULES 审中-公开
标题翻译：存储器件中存储器件的独立打包
公开(公告)号：WO2009137157A1
公开(公告)日：2009-11-12
申请号：PCT/US2009/036161
申请日：2009-03-05
申请人： RAMBUS INC. , WARE, Frederick, A. , HAMPEL, Craig, E. , SHAEFFER, Ian , BEST, Scott, C.
发明人： WARE, Frederick, A. , HAMPEL, Craig, E. , SHAEFFER, Ian , BEST, Scott, C.
IPC分类号： G06F13/16 , G06F13/42 , G11C7/00 , G11C5/00
CPC分类号： G11C7/1072 , G06F13/1684 , G06F13/4234 , G11C5/00
摘要： A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command.
摘要翻译：存储器模块包括其上具有信号线的衬底，其形成控制路径和多个数据路径。多个存储器件安装在基片上。每个存储器件耦合到控制路径和不同的数据路径。存储器模块包括控制电路，以使得每个存储器设备能够在一系列存储器访问命令中处理不同的相应存储器访问命令，并且响应于处理的存储器访问命令在不同的数据路径上输出数据。

7. 发明申请

WO2006062569A2 MEMORY INTERFACE WITH WORKLOAD ADAPTIVE ENCODE/DECODE 审中-公开
标题翻译：具有工作自适应编码/解码的记忆接口
公开(公告)号：WO2006062569A2
公开(公告)日：2006-06-15
申请号：PCT/US2005/034264
申请日：2005-09-26
申请人： RAMBUS INC. , HAMPEL, Craig, E.
发明人： HAMPEL, Craig, E.
IPC分类号： G06F13/16
CPC分类号： G06F13/1668
摘要： A communication interface ( e.g ., a memory interface) includes a data processing channel adapted to be coupled to a data source and having multiple data processing stages. A bypass network or pipeline is coupled to the data processing channel and configurable to bypass at least one stage in the data processing channel. A controller is coupled to the bypass network for configuring the bypass network to bypass at least one stage of the data processing channel based on performance criteria. In some embodiments or modes of operation, the bypass network is configured to bypass at least one stage of the data processing channel to reduce idle latency after an idle period. In an alternative embodiment or mode of operation, the bypass channel is configured to include at least one stage of the data processing channel to increase data throughput.
摘要翻译：通信接口（例如，存储器接口）包括适于耦合到数据源并具有多个数据处理阶段的数据处理通道。旁路网络或管线耦合到数据处理通道并且可配置为绕过数据处理通道中的至少一个级。控制器耦合到旁路网络，用于基于性能标准配置旁路网络以绕过数据处理信道的至少一个级。在一些实施例或操作模式中，旁路网络被配置为绕过数据处理信道的至少一个级，以在空闲周期之后减少空闲等待时间。在替代实施例或操作模式中，旁路通道被配置为包括数据处理通道的至少一个级以增加数据吞吐量。

8. 发明申请

WO2005033958A1 INTEGRATED CIRCUIT WITH BI-MODAL DATA STROBE 审中-公开
标题翻译：具有双模态数据结构的集成电路
公开(公告)号：WO2005033958A1
公开(公告)日：2005-04-14
申请号：PCT/US2004/029186
申请日：2004-09-03
申请人： RAMBUS INC. , HAMPEL, Craig, E.
发明人： HAMPEL, Craig, E.
IPC分类号： G06F13/16
CPC分类号： G06F13/1694 , G06F13/1689
摘要： A memory device that has two operating modes. In the first mode the data strobe is source synchronous and is driven by the memory device when data is being transmitted. In the second mode the data strobe is not driven by the memory device. In this mode the data strobe signal is used as a free running clock to sample write data. The capture of read data by the controller is timed by the controller with a calibrated internal timing reference from the system clock.
摘要翻译：具有两种操作模式的存储设备。在第一模式中，数据选通是源同步的，并且当数据被发送时由存储器件驱动。在第二模式中，数据选通不由存储器件驱动。在此模式下，数据选通信号用作自由运行时钟来采样写入数据。由控制器捕获读取数据由控制器定时，系统时钟具有校准的内部定时参考。

9. 发明申请

WO2016089563A1 HIGH PERFORMANCE, HIGH CAPACITY MEMORY SYSTEMS AND MODULES 审中-公开
标题翻译：高性能，高容量存储系统和模块
公开(公告)号：WO2016089563A1
公开(公告)日：2016-06-09
申请号：PCT/US2015/060057
申请日：2015-11-11
申请人： RAMBUS INC.
发明人： WARE, Frederick, A. , TSERN, Ely , LINSTADT, John, Eric , GIOVANNINI, Thomas, J. , HAMPEL, Craig, E. , BEST, Scott, C. , YAN, John
IPC分类号： G06F13/16 , G11C7/10
CPC分类号： G06F13/1678 , G06F13/1673 , G06F13/1694
摘要： Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility, or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.
摘要翻译：描述的是具有内存模块插槽的主板，它们接受传统内存模块以实现向后兼容，或接受更多数量的可配置模块以支持增加的内存容量。可配置模块可以与传统主板向后兼容。配有可配置模块，主板支持高信令速率和容量的内存系统。

10. 发明申请

WO2007106710A2 MEMORY DEVICE WITH MODE-SELECTABLE PREFETCH AND CLOCK-TO-CORE TIMING 审中-公开
标题翻译：具有模式选择性预设和时钟到核心时序的存储器件
公开(公告)号：WO2007106710A2
公开(公告)日：2007-09-20
申请号：PCT/US2007/063567
申请日：2007-03-08
申请人： RAMBUS INC. , BELLOWS, Chad, A. , HAMPEL, Craig, E.
发明人： BELLOWS, Chad, A. , HAMPEL, Craig, E.
CPC分类号： G11C7/1039 , G11C7/1012 , G11C7/1042 , G11C7/1051 , G11C7/1066 , G11C2207/107
摘要： In a memory device, either a first portion or a second, smaller portion of data retrieved from a storage array is loaded into a data buffer in accordance with a prefetch mode selection and then output from the memory device via a signaling interface. A value that indicates a minimum number of cycles of a clock signal that are to transpire between successive accesses to any one of the storage resources may be received and stored within a configuration circuit of the memory device. If the value indicates a number of clock cycles, N, that is less than a threshold number, the memory device may transfer data associated with a first address between the signaling interface and the data buffer during each of N cycles of the clock signal. If N is greater than or equal to the threshold number, the memory device may transfer the data associated with the first address between the signaling interface and the storage buffer during each of X cycles of the clock signal, and then transfer data associated with the second address between the signaling interface and the storage buffer during each of X cycles of the clock signal, where X is an integer value less than N.
摘要翻译：在存储器件中，根据预取模式选择将从存储阵列检索的数据的第一部分或第二较小部分的数据加载到数据缓冲器中，然后经由信令接口从存储器件输出。指示在对任何一个存储资源的连续访问之间发生的时钟信号的最小周期数的值可以被接收并存储在存储器件的配置电路中。如果该值指示小于阈值数目的时钟周期数N，那么存储器件可以在时钟信号的N个周期的每个周期期间传送与信令接口和数据缓冲器之间的第一地址相关联的数据。如果N大于或等于阈值数，则在时钟信号的X个周期的每个周期期间，存储器件可以传送与信令接口和存储缓冲器之间的第一地址相关联的数据，然后传送与第二个在时钟信号的X个周期的每个周期期间，信令接口和存储缓冲器之间的地址，其中X是小于N的整数值。

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