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1. 发明申请

WO2009137157A1 INDEPENDENT THREADING OF MEMORY DEVICES DISPOSED ON MEMORY MODULES 审中-公开
标题翻译：存储器件中存储器件的独立打包
公开(公告)号：WO2009137157A1
公开(公告)日：2009-11-12
申请号：PCT/US2009/036161
申请日：2009-03-05
申请人： RAMBUS INC. , WARE, Frederick, A. , HAMPEL, Craig, E. , SHAEFFER, Ian , BEST, Scott, C.
发明人： WARE, Frederick, A. , HAMPEL, Craig, E. , SHAEFFER, Ian , BEST, Scott, C.
IPC分类号： G06F13/16 , G06F13/42 , G11C7/00 , G11C5/00
CPC分类号： G11C7/1072 , G06F13/1684 , G06F13/4234 , G11C5/00
摘要： A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command.
摘要翻译：存储器模块包括其上具有信号线的衬底，其形成控制路径和多个数据路径。多个存储器件安装在基片上。每个存储器件耦合到控制路径和不同的数据路径。存储器模块包括控制电路，以使得每个存储器设备能够在一系列存储器访问命令中处理不同的相应存储器访问命令，并且响应于处理的存储器访问命令在不同的数据路径上输出数据。

2. 发明申请

WO2012145117A2 MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES 审中-公开
标题翻译：存储器组件和控制器，用于校准多个同步时序参考
公开(公告)号：WO2012145117A2
公开(公告)日：2012-10-26
申请号：PCT/US2012/029893
申请日：2012-03-21
申请人： RAMBUS INC. , GIOVANNINI, Thomas, J. , BEST, Scott, C. , LUO, Lei , SHAEFFER, Ian
发明人： GIOVANNINI, Thomas, J. , BEST, Scott, C. , LUO, Lei , SHAEFFER, Ian
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/227 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C29/56
摘要： A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.
摘要翻译：第一定时参考信号和第二定时参考信号被发送到存储器件。第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。从存储装置接收多个串行数据模式。第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。时间指示器均使用单个采样器进行测量。基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

3. 发明申请

WO2011106056A1 METHODS AND CIRCUITS FOR DYNAMICALLY SCALING DRAM POWER AND PERFORMANCE 审中-公开
标题翻译：用于动态调整DRAM功率和性能的方法和电路
公开(公告)号：WO2011106056A1
公开(公告)日：2011-09-01
申请号：PCT/US2010/058555
申请日：2010-12-01
申请人： RAMBUS INC. , TSERN, Ely , VOGELSANG, Thomas , HAMPEL, Craig , BEST, Scott, C.
发明人： TSERN, Ely , VOGELSANG, Thomas , HAMPEL, Craig , BEST, Scott, C.
IPC分类号： G11C11/4074 , G11C11/4063 , G11C11/408 , G06F13/14
CPC分类号： G06F3/0625 , G06F1/266 , G06F3/0634 , G06F3/0673 , G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.
摘要翻译：内存系统支持高性能和低功耗模式。存储器系统包括存储器核和核心接口。存储器内核采用在两种模式下保持相同的核心电源电压。核心接口的电源电压和信号速率可以缩小以节省功耗。存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

4. 发明申请

WO2005089407A2 DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS 审中-公开
标题翻译：用于通信信道的跟踪跟踪反馈
公开(公告)号：WO2005089407A2
公开(公告)日：2005-09-29
申请号：PCT/US2005/008830
申请日：2005-03-16
申请人： RAMBUS, INC. , BEST, Scott, C. , ABHYANKAR, Abhijit, M. , CHANG, Kun-Yung , LAMBRECHT, Frank
发明人： BEST, Scott, C. , ABHYANKAR, Abhijit, M. , CHANG, Kun-Yung , LAMBRECHT, Frank
IPC分类号： G06F1/04 , H04L7/00 , H04L7/10 , H04L25/14
CPC分类号： G06F1/08 , G06F1/12 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , H04L7/0004 , H04L7/0008 , H04L7/0033 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/14
摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.
摘要翻译：通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。通信链路耦合第一和第二组件。校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要响应监控功能。

5. 发明申请

WO2004109702A1 ADJUSTABLE CLOCK DRIVER CIRCUIT 审中-公开
标题翻译：可调节时钟驱动电路
公开(公告)号：WO2004109702A1
公开(公告)日：2004-12-16
申请号：PCT/US2004/018226
申请日：2004-06-03
申请人： RAMBUS INC. , BEST, Scott, C. , LAMBRECHT, Frank
发明人： BEST, Scott, C. , LAMBRECHT, Frank
IPC分类号： G11C7/22
CPC分类号： G11C7/222 , G06F13/1689 , G11C7/04 , G11C7/22 , Y02D10/14
摘要： Disclosed is a circuit for generating a clock signal to driver a plurality of memory components in a memory subsystern. The clock driver circuit comprises a clock generator for transmitting a clock signal to drive the plurality of memory components, a memory controller for controlling the plurality of memory components, and an adjustable impedance circuit residing within said memory controller such that the adjustable impedance circuit is programmable in accordance with a control input generated by the memory controller. The clock generator is configured to generate a clock signal with a voltage swing controlled by the impedance of the adjustable impedance circuit.
摘要翻译：公开了一种用于产生时钟信号以驱动存储器子体中的多个存储器组件的电路。时钟驱动器电路包括用于传输时钟信号以驱动多个存储器组件的时钟发生器，用于控制多个存储器组件的存储器控制器和驻留在所述存储器控制器内的可调阻抗电路，使得可调阻抗电路是可编程的根据存储器控制器产生的控制输入。时钟发生器被配置为产生具有由可调阻抗电路的阻抗控制的电压摆幅的时钟信号。

6. 发明申请

WO2007064785A2 PULSED SIGNALING MULTIPLEXER 审中-公开
标题翻译：脉冲信号多路复用器
公开(公告)号：WO2007064785A2
公开(公告)日：2007-06-07
申请号：PCT/US2006/045830
申请日：2006-11-30
申请人： RAMBUS INC. , BEST, Scott, C.
发明人： BEST, Scott, C.
IPC分类号： H03M9/00
CPC分类号： H04J3/02 , H04J3/047 , H04L25/028 , H04L25/493
摘要： In one embodiment, a pulsed signaling multiplexer is described that comprises a first AC-coupled transmitter and a second AC-coupled transmitter. The first AC-coupled transmitter includes a first driver having a first input to receive first data and a first output. A first AC-coupling element couples the first output to a common output node. The second AC-coupled transmitter includes a second driver having a second input to receive second data, and a second output. A second AC-coupling element couples the second output to the same first common output node.
摘要翻译：在一个实施例中，描述了包括第一AC耦合发射机和第二AC耦合发射机的脉冲信令多路复用器。第一AC耦合发射机包括具有用于接收第一数据和第一输出的第一输入的第一驱动器。第一AC耦合元件将第一输出耦合到公共输出节点。第二AC耦合发射机包括具有用于接收第二数据的第二输入的第二驱动器和第二输出。第二AC耦合元件将第二输出耦合到相同的第一公共输出节点。

7. 发明申请

WO2006099147A1 SELF-TIMED INTERFACE FOR STROBE-BASED SYSTEMS 审中-公开
标题翻译：用于基于STROBE的系统的自定义接口
公开(公告)号：WO2006099147A1
公开(公告)日：2006-09-21
申请号：PCT/US2006/008610
申请日：2006-03-10
申请人： RAMBUS INC. , BEST, Scott, C. , KIZER, Jade, M.
发明人： BEST, Scott, C. , KIZER, Jade, M.
IPC分类号： G06F13/40 , G06F13/38 , G06F5/06
CPC分类号： G06F13/4059
摘要： Self-timed interfaces and methods are provided for interfacing different timing domains. These self-timed interfaces receive a strobe signal from a component operating under a first clock domain. A first signal path of the self-timed interface couples the strobe signal to a receiver that samples data of data line under control of the strobe signal. A second signal path of the self-timed interface couples the strobe signal to an interface circuit through a hysteresis-based element. The interface circuit, under control of an output of the hysteresis-based element along with a clock signal that originates under a second clock domain, generates an interface enable signal for use in controlling data transfers between the different clock domains.
摘要翻译：提供自定义接口和方法来连接不同的定时域。这些自定时接口从在第一时钟域下运行的组件接收选通信号。自定时接口的第一信号路径将选通信号耦合到在选通信号的控制下采样数据线的数据的接收机。自定时接口的第二信号路径通过基于滞后的元件将选通信号耦合到接口电路。接口电路在基于滞后的元件的输出的控制下以及起始于第二时钟域的时钟信号产生用于控制不同时钟域之间的数据传输的接口使能信号。

8. 发明申请

WO2012021310A1 DISAGGREGATED SEMICONDUCTOR CHIP ASSEMBLY AND PACKAGING TECHNIQUE 审中-公开
标题翻译：分散式半导体芯片组装和包装技术
公开(公告)号：WO2012021310A1
公开(公告)日：2012-02-16
申请号：PCT/US2011/045920
申请日：2011-07-29
申请人： RAMBUS INC. , BEST, Scott, C.
发明人： BEST, Scott, C.
IPC分类号： H01L23/52
CPC分类号： H01L23/49816 , H01L23/481 , H01L23/525 , H01L25/18 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06544 , H01L2924/10253 , H01L2924/15311 , H01L2924/19107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor package is disclosed. The package comprises a substrate having terminals for external connections and respective first and second semiconductor chips. The first semiconductor chip has pads coupled to respective ones of the terminals and includes a metal layer. The second semiconductor chip is attached to the first semiconductor chip and has first contacts electrically coupled to respective ones of the pads through the metal layer. The second semiconductor chip overlying an area of the first semiconductor chip that is less than a surface area occupied by the pads.
摘要翻译：公开了半导体封装。该封装包括具有用于外部连接的端子和相应的第一和第二半导体芯片的基板。第一半导体芯片具有耦合到相应端子的焊盘并且包括金属层。第二半导体芯片附接到第一半导体芯片，并且具有通过金属层电耦合到各个焊盘的第一触点。覆盖第一半导体芯片的区域的第二半导体芯片小于由焊盘占据的表面积。

9. 发明申请

WO2010138480A2 STACKED SEMICONDUCTOR DEVICE ASSEMBLY 审中-公开
标题翻译：堆叠半导体器件组件
公开(公告)号：WO2010138480A2
公开(公告)日：2010-12-02
申请号：PCT/US2010/036020
申请日：2010-05-25
申请人： RAMBUS INC. , BEST, Scott, C.
发明人： BEST, Scott, C.
IPC分类号： H01L23/60
CPC分类号： G06F13/362 , G06F13/4068 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C14/0018 , G11C16/10 , G11C16/26 , H01L23/48 , H01L23/481 , H01L23/50 , H01L23/60 , H01L24/09 , H01L25/0652 , H01L25/0657 , H01L27/0248 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/08145 , H01L2224/16145 , H01L2224/16225 , H01L2225/06503 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2924/1436 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： The semiconductor device system includes multiple stacked substantially identical semiconductor devices each including a first side and an opposing second side. First and second pads are disposed at the first side of the semiconductor device, while third and fourth pads are disposed at the second side of the semiconductor device. First interface circuit is electrically coupled to the first pad and the third pad, while second interface circuit is electrically coupled to the second pad and the fourth pad. The second interface circuit is separate and distinct from the first interface circuit. At least one first semiconductor device of the multiple semiconductor devices is offset from other of the multiple semiconductor devices such that the fourth pad on the first semiconductor device is aligned with, and electrically connected to, the first pad on an adjacent one of the multiple semiconductor devices. In some embodiments, the first pad is associated with a first capacitance, while the second pad is associated with a second capacitance that is smaller than the first capacitance.
摘要翻译：半导体器件系统包括多个层叠的基本相同的半导体器件，每个半导体器件包括第一侧和相对的第二侧。第一和第二焊盘设置在半导体器件的第一侧，而第三和第四焊盘设置在半导体器件的第二侧。第一接口电路电耦合到第一焊盘和第三焊盘，而第二接口电路电耦合到第二焊盘和第四焊盘。第二接口电路与第一接口电路分离并且不同。多个半导体器件中的至少一个第一半导体器件偏离多个半导体器件中的其它半导体器件，使得第一半导体器件上的第四焊盘与多个半导体器件中相邻的半导体器件上的第一焊盘对准并电连接到第一焊盘设备。在一些实施例中，第一焊盘与第一电容相关联，而第二焊盘与小于第一电容的第二电容相关联。

10. 发明申请

WO2011025557A1 FORWARDING SIGNAL SUPPLY VOLTAGE IN DATA TRANSMISSION SYSTEM 审中-公开
标题翻译：数据传输系统中的前向信号供电电压
公开(公告)号：WO2011025557A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/029252
申请日：2010-03-30
申请人： RAMBUS INC. , BEST, Scott, C. , POULTON, John, W.
发明人： BEST, Scott, C. , POULTON, John, W.
IPC分类号： G11C5/14 , G06F13/40 , G11C7/10
CPC分类号： G11C5/144 , G06F11/0727 , G06F11/076 , G06F11/0793 , G06F13/4072 , G11C5/145 , H04L1/203 , H04L25/0264 , H04L25/08
摘要： In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.
摘要翻译：在数据传输系统中，在第一电路中生成用于产生要发送的信号的信令电压的一个或多个信号电源电压，并从第一电路转发到第二电路。第二电路可以使用转发的信号电源电压来产生要从第二电路传输回第一电路的另一个信号，从而避免在第二电路中单独产生信号电源电压的需要。第一电路还可以基于从第二电路传输回第一电路的信号来调整信号电源电压。数据传输系统可以使用单端信令系统，其中信令电压参考作为由第一电路和第二电路共享的诸如地的电源电压的参考电压。

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