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1. 发明申请

WO2003036445A1 TIMING CALIBRATION APPARATUS AND METHOD FOR A MEMORY DEVICE SIGNALING SYSTEM 审中-公开
标题翻译：用于记忆装置信号系统的时序校准装置和方法
公开(公告)号：WO2003036445A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/033707
申请日：2002-10-22
申请人： RAMBUS INC.
发明人： HAMPEL, Craig, E. , PEREGO, Richard, E. , SIDIROPOULOS, Stephanos, S. , TSERN, Ely, K. , WARE, Fredrick, A.
IPC分类号： G06F1/12
CPC分类号： G11C11/4076 , G06F3/061 , G06F3/0629 , G06F3/0671 , G06F12/0246 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4072 , G11C11/4078 , G11C11/4093 , G11C21/00 , G11C2207/2254 , H04L7/0025 , H04L7/0079 , H04L7/0091
摘要： A memory system includes a memory controller (405) and a memory component (410) coupled to each other. An interface of the memory component (410) is configured to receive a first signal from the memory controller (410) with read request information, retrieve the read data information (410) from the memory core in response to the request information, and transmit to the memory controller (410) a second signal containing the read data information. The read data information includes read data symbols, where the average duration of the read data symbols, measured at the interface, defines a symbol time interval. A first external access time is measured at the interface between a first read request and read data transmitted by the interface in response to the first read request. A second external access time interval is measured at the interface between a second read request and read data transmitted by the interface in response to the second read request. The difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.
摘要翻译：存储器系统包括彼此耦合的存储器控制器（405）和存储器组件（410）。存储器组件（410）的接口被配置为用读取请求信息从存储器控制器（410）接收第一信号，响应于请求信息从存储器核心检索读取的数据信息（410），并且发送到存储器控制器（410）包含读取的数据信息的第二信号。读数据信息包括读数据符号，其中在接口处测量的读数据符号的平均持续时间定义符号时间间隔。在第一读取请求和由接口响应于第一读取请求而发送的读取数据之间的接口处测量第一外部访问时间。第二外部访问时间间隔在响应于第二读取请求的第二读取请求和由接口发送的读取数据之间的接口处被测量。第一外部访问时间和第二外部访问时间之间的差异大于符号时间间隔的一半。

2. 发明申请

WO1998028746A1 REDUNDANCY FOR WIDE HIERARCHICAL I/O ORGANIZATIONS 审中-公开
标题翻译：冗长的分层I / O组织
公开(公告)号：WO1998028746A1
公开(公告)日：1998-07-02
申请号：PCT/US1997024095
申请日：1997-12-22
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , STARK, Donald, C. , TSERN, Ely, K.
IPC分类号： G11C07/00
CPC分类号： G11C29/848
摘要： In a memory core (Figure 3) a method and apparatus for replacing global I/O lines (56, 58, Figure 3) associated with a defective column in a memory sub-array with global I/O lines not associated with such a defect. To improve yield of a memory device such as a DRAM, the device typically employs spare elements which can replace defective elements. In this invention, to reduce the die area consumed for spare elements, the global I/O line (56, 58, Figure 3) is chosen as the replaceable element. The bit position of a defective global I/O line within a bus of global I/O lines is determined. According to whether a particular column has a defect and for each normal global I/O line with a defective column, the global I/O line is replaced with an adjacent non-defective global I/O line (Figure 5). At the bit position a spare on-defective global I/O line is introduced to complete the bus. The number of defective global I/O lines that may be removed from the bus is the same as the number of spare non-defective I/O lines (40, Figure 3) available to fill in the missing bit positions at the end of the bus.
摘要翻译：在存储器核心（图3）中，用于替换与存储器子阵列中与缺陷列相关联的全局I / O线（56,58，图3）的方法和装置，其中全局I / O线与这种缺陷无关。为了提高诸如DRAM的存储器件的产量，该器件通常采用可替代有缺陷元件的备用元件。在本发明中，为了减少备用元件消耗的管芯面积，选择全局I / O管线（56,58，图3）作为可更换元件。确定全局I / O线总线内缺陷全局I / O线的位位置。根据特定列是否有缺陷，并且对于具有缺陷列的每个正常全局I / O线，全局I / O线将被替换为相邻的无缺陷全局I / O线（图5）。在位位置，引入备用缺陷全局I / O线来完成总线。可以从总线中删除的缺陷全局I / O线的数量与可用于填充末尾的丢失位位置的备用无缺陷I / O线（40，图3）的数量相同总线。

3. 发明申请

WO2006132840A2 MEMORY SYSTEM WITH ERROR DETECTION AND RETRY MODES OF OPERATION 审中-公开
标题翻译：具有错误检测和重新运行模式的记忆系统
公开(公告)号：WO2006132840A2
公开(公告)日：2006-12-14
申请号：PCT/US2006/020698
申请日：2006-05-26
申请人： RAMBUS INC. , TSERN, Ely, K. , HOROWITZ, Mark, A. , WARE, Frederick, A.
发明人： TSERN, Ely, K. , HOROWITZ, Mark, A. , WARE, Frederick, A.
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A system and method for inductively heating a work piece. The induction heating system is coupleable to a plurality of temperature feedback devices operable to provide a signal representative of work piece temperature. The induction heating system is operable to control the output of the induction heating system based on the plurality of signals representative of work piece temperature received from the plurality of temperature feedback devices.
摘要翻译：一种用于感应加热工件的系统和方法。感应加热系统可耦合到可操作以提供表示工件温度的信号的多个温度反馈装置。感应加热系统可操作以基于代表从多个温度反馈装置接收的工件温度的多个信号来控制感应加热系统的输出。

4. 发明申请

WO2002071407A3 ASYNCHRONOUS, HIGH-BANDWIDTH MEMORY COMPONENT USING CALIBRATED TIMING ELEMENTS 审中-公开
公开(公告)号：WO2002071407A3
公开(公告)日：2002-09-12
申请号：PCT/US2002/002597
申请日：2002-01-30
申请人： RAMBUS, INC.
发明人： WARE, Frederick, A. , TSERN, Ely, K. , HAMPEL, Craig, E. , STARK, Donald, C.
IPC分类号： G11C7/10
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different synchronous delays and to strobe sequential pipeline elements of the memory device.

5. 发明申请

WO2007019297A1 MEMORY WITH ADDRESS-DIFFERENTIATED REFRESH RATE TO ACCOMMODATE LOW-RETENTION STORAGE ROWS 审中-公开
标题翻译：具有地址差异刷新率的存储器来保存低保持存储区
公开(公告)号：WO2007019297A1
公开(公告)日：2007-02-15
申请号：PCT/US2006/030413
申请日：2006-08-03
申请人： RAMBUS INC. , TSERN, Ely, K.
发明人： TSERN, Ely, K.
IPC分类号： G11C11/406
CPC分类号： G11C11/40611 , G11C11/406 , G11C29/023 , G11C29/028 , G11C29/50016 , G11C2211/4061
摘要： In a dynamic random access memory device, receiving refresh commands via a signaling interface and, in response to the refresh commands, refreshing a first row of storage cells at a first refresh rate and refreshing a second row of storage cells at a second, faster refresh rate.
摘要翻译：在动态随机存取存储器装置中，经由信令接口接收刷新命令，并且响应于所述刷新命令，以第一刷新率刷新第一行存储单元，并以第二更新刷新刷新第二行存储单元率。

6. 发明申请

WO2004001574A1 METHOD AND APPARATUS FOR THE DYNAMIC SCHEDULING OF DEVICE COMMANDS 审中-公开
标题翻译：用于设备命令动态调度的方法和装置
公开(公告)号：WO2004001574A1
公开(公告)日：2003-12-31
申请号：PCT/US2003/019802
申请日：2003-06-20
申请人： RAMBUS INC.
发明人： PEREGO, Richard, E. , WARE, Frederick, A. , HAMPEL, Craig, E. , TSERN, Ely, K.
IPC分类号： G06F3/00
CPC分类号： G06F13/1605
摘要： Methods and apparatuses for scheduling commands are described. According to various embodiments of the invention ,delay information (108, 112), is issued with an associated command (101, 103). The delay information (201, 206) directs the device for which the command is intended to either execute the command immediately or to delay the command for some period of time before execution. Multiple commands (207) can be queued for execution within the device (202, 203, 204).
摘要翻译：描述用于调度命令的方法和装置。根据本发明的各种实施例，发出具有相关命令（101,103）的延迟信息（108,112）。所述延迟信息（201,206）指示所述命令旨在的设备或者立即执行该命令，或者在执行之前延迟该命令一段时间。多个命令（207）可以排队等待在设备（202,203,204）内执行。

7. 发明公开

EP1397807A2 ASYNCHRONOUS, HIGH-BANDWIDTH MEMORY COMPONENT USING CALIBRATED TIMING ELEMENTS 审中-公开
标题翻译：校准延迟元素具有高带宽内存异步组件
公开(公告)号：EP1397807A2
公开(公告)日：2004-03-17
申请号：EP02726564.4
申请日：2002-01-30
申请人： Rambus, Inc.
发明人： WARE, Frederick, A. , TSERN, Ely, K. , HAMPEL, Craig, E. , STARK, Donald, C.
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different synchronous delays and to strobe sequential pipeline elements of the memory device.

8. 发明授权

EP1446910B1 PHASE ADJUSTMENT APPARATUS AND METHOD FOR A MEMORY DEVICE SIGNALING SYSTEM 有权
标题翻译：移相器和方法内存模块信令系统
公开(公告)号：EP1446910B1
公开(公告)日：2010-08-11
申请号：EP02802180.6
申请日：2002-10-22
申请人： RAMBUS INC.
发明人： HAMPEL, Craig, E. , PEREGO, Richard, E. , SIDIROPOULOS, Stephanos, S. , TSERN, Ely, K. , WARE, Fredrick, A.
IPC分类号： H04L5/16 , G06F1/04 , G11C7/10
CPC分类号： G11C11/4076 , G06F3/061 , G06F3/0629 , G06F3/0671 , G06F12/0246 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4072 , G11C11/4078 , G11C11/4093 , G11C21/00 , G11C2207/2254 , H04L7/0025 , H04L7/0079 , H04L7/0091
摘要： A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset.

9. 发明公开

EP1446910A1 PHASE ADJUSTMENT APPARATUS AND METHOD FOR A MEMORY DEVICE SIGNALING SYSTEM 有权
标题翻译：移相器和方法内存模块信令系统
公开(公告)号：EP1446910A1
公开(公告)日：2004-08-18
申请号：EP02802180.6
申请日：2002-10-22
申请人： Rambus Inc.
发明人： HAMPEL, Craig, E. , PEREGO, Richard, E. , SIDIROPOULOS, Stephanos, S. , TSERN, Ely, K. , WARE, Fredrick, A.
IPC分类号： H04L5/16 , G06F1/04
CPC分类号： G11C11/4076 , G06F3/061 , G06F3/0629 , G06F3/0671 , G06F12/0246 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4072 , G11C11/4078 , G11C11/4093 , G11C21/00 , G11C2207/2254 , H04L7/0025 , H04L7/0079 , H04L7/0091
摘要： A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset.

10. 发明公开

EP0948792A1 METHOD AND APPARATUS FOR SHARING SENSE AMPLIFIERS BETWEEN MEMORY BANKS 无效
标题翻译：用于读取放大器的使用方法和系统锁存存储
公开(公告)号：EP0948792A1
公开(公告)日：1999-10-13
申请号：EP97953233.0
申请日：1997-12-17
申请人： Rambus, Inc.
发明人： BARTH, Richard, M. , STARK, Donald, C. , TSERN, Ely, K.
IPC分类号： G11C7 , G11C11
CPC分类号： G11C7/06 , G11C7/00 , G11C11/409
摘要： A memory device includes a first memory bank and a second memory bank, each memory bank having at least one subarray of memory cells. Multiple sense amplifiers are coupled to both the first memory bank and the second memory bank. The multiple sense amplifiers are configured for use by both the first memory bank and the second memory bank, but not simultaneously. A control mechanism is used to avoid accessing the first memory bank and the second memory bank simultaneously. The sharing of sense amplifiers between memory banks minimizes the die area penalty caused by additional memory banks.

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