专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120136889A1 Hash Collision Resolution with Key Compression in a MAC Forwarding Data Structure 有权
标题翻译： MAC转发数据结构中的密钥压缩的哈希碰撞解决方案
公开(公告)号：US20120136889A1
公开(公告)日：2012-05-31
申请号：US12957301
申请日：2010-11-30
申请人： RAJESH JAGANNATHAN , BRIAN ALLEYNE , RAMANATHAN LAKSHMIKANTHAN
发明人： RAJESH JAGANNATHAN , BRIAN ALLEYNE , RAMANATHAN LAKSHMIKANTHAN
IPC分类号： G06F17/30
CPC分类号： H04L49/3009
摘要： Embodiments of the invention include a method performed in a media access control (MAC) forwarding control module within a network element for looking up a MAC address and interface (I/F) identifier pair (MAC-I/F pair) from a MAC forwarding data structure that comprises a first tier data structure and a plurality of second tier data structures. The MAC forwarding data structure utilizes compressed keys to index each of the plurality second tier data structures. The compressed key is generated with a desired MAC address and a mask bit list that corresponds with enough bit positions such that all MAC addresses in second tier data structure can be uniquely addressed with just the values of each MAC address in the bit positions listed. As such, the MAC forwarding data structure is constructed so that the total cost of a lookup with the compressed key technique is deterministic and, therefore, O(1).
摘要翻译：本发明的实施例包括在网络单元内的媒体访问控制（MAC）转发控制模块中执行的方法，用于从MAC转发查找MAC地址和接口（I / F）标识符对（I / F）标识符对（MAC-I / F对）包括第一层数据结构和多个第二层数据结构的数据结构。 MAC转发数据结构利用压缩密钥来索引多个第二层数据结构中的每一个。使用所需的MAC地址和与足够的位位置相对应的掩码位列来生成压缩密钥，使得可以仅仅列出所述位位置中的每个MAC地址的值来唯一地寻址第二层数据结构中的所有MAC地址。因此，MAC转发数据结构被构造成使得具有压缩密钥技术的查找的总成本是确定性的，并且因此是O（1）。

2. 发明申请

US20120170472A1 ON-CHIP PACKET CUT-THROUGH 有权
标题翻译：片上包裹切割
公开(公告)号：US20120170472A1
公开(公告)日：2012-07-05
申请号：US12983104
申请日：2010-12-31
申请人： EDMUND CHEN , RAMANATHAN LAKSHMIKANTHAN , RANJIT ROZARIO , BRIAN ALLEYNE , STEPHEN CHOW , PATRICK WANG , EDWARD HO , THOMAS YIP , SUN DEN CHEN , MICHAEL FENG
发明人： EDMUND CHEN , RAMANATHAN LAKSHMIKANTHAN , RANJIT ROZARIO , BRIAN ALLEYNE , STEPHEN CHOW , PATRICK WANG , EDWARD HO , THOMAS YIP , SUN DEN CHEN , MICHAEL FENG
IPC分类号： H04L12/56 , H04L12/26
CPC分类号： H04L49/9073 , H04L47/12 , H04L47/2441 , H04L47/32 , H04L49/9036 , H04L49/9063 , H04L49/9078
摘要： Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.
摘要翻译：本发明的实施例包括一种在分组处理期间避免存储器带宽利用的方法。分组处理核心接收多个分组。分组处理核心识别分组的服务质量（QoS）描述符。分组处理核心确定至少一个分组应该被移动到在分组被发送到出口端口之前存储的片外分组。分组处理核心基于至少部分地确定分组的QoS描述符。分组处理核心将确定的分组移动到片外分组存储。分组处理核心在分组被发送到出口端口之前确定至少一个分组不应该被移动到片外分组存储。该决定至少部分地基于分组的QoS描述符进行。

3. 发明申请

US20120170450A1 HIERARCHICAL PACKET POLICER 有权
标题翻译：分层分组策略器
公开(公告)号：US20120170450A1
公开(公告)日：2012-07-05
申请号：US12983111
申请日：2010-12-31
申请人： BRIAN ALLEYNE , SUNDEN CHEN , RAMANATHAN LAKSHMIKANTHAN
发明人： BRIAN ALLEYNE , SUNDEN CHEN , RAMANATHAN LAKSHMIKANTHAN
IPC分类号： H04L12/26
CPC分类号： H04L47/20 , H04L47/215 , H04L47/31
摘要： Embodiments of the invention include a method performed in a packet processor core for policing a packet through a hierarchical policer coupled to one or more policing requestors. The hierarchical policer has a plurality of meter levels including an initial level and one or more subsequent levels. The hierarchical policer creates a meter result at the meter of each meter level using packet characteristics and a meter state for that meter level. The hierarchical policer generates meter level outputs that classify the packet for each meter level and for at least one of the subsequent levels the meter level output is based on the meter level output from a previous meter level. The hierarchical policer performs a meter combine operation that produces a final packet output attribute from the combination of the meter level outputs. The hierarchical policer returns the final packet output attribute to a policing requestor.
摘要翻译：本发明的实施例包括在分组处理器核心中执行的方法，用于通过耦合到一个或多个管理请求者的分级策略器来管理分组。分层监视器具有包括初始级别和一个或多个后续级别的多个仪表级别。分层监视器使用分组特性和该仪表级的仪表状态在每个仪表级的仪表处创建仪表结果。分层监视器产生仪表级输出，对每个仪表级进行分组，对于至少一个后续级别，仪表电平输出基于从先前仪表级别输出的仪表电平。分层监视器执行仪表组合操作，其从仪表级输出的组合产生最终的分组输出属性。分层策略器将最终的分组输出属性返回给管理请求者。

4. 发明申请

US20120079228A1 DIGITAL COUNTER SEGMENTED INTO SHORT AND LONG ACCESS TIME MEMORY 有权
标题翻译：数字计数器分为短暂和长时间访问时间记忆
公开(公告)号：US20120079228A1
公开(公告)日：2012-03-29
申请号：US12890479
申请日：2010-09-24
申请人： EDMUND G. CHEN , BRIAN ALLEYNE , ROBERT HATHAWAY , RANJIT J. ROZARIO , TODD D. BASSO
发明人： EDMUND G. CHEN , BRIAN ALLEYNE , ROBERT HATHAWAY , RANJIT J. ROZARIO , TODD D. BASSO
IPC分类号： G06F12/00
CPC分类号： H03K21/38 , H03K21/16
摘要： A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
摘要翻译：一种在存储器控制器中执行的方法，用于将分段计数器分为主存储器和次存储器，主存储器更快。发生需要增加分段计数器之一并且存储器控制器通过增加主存储器中的相应主要部分来进行响应的事件。每次主要部件在内存控制器上滚动时，都会确定应该更新次要部件。此外，存储器控制器周期性地确定分段计数器的次要部分应该被机会性地更新。机会更新是基于概率函数和随机数。辅助部分至少包括不在主要部分中的分段计数器的所有位，并存储在辅助存储器中。每次发生对次要部件的更新时，分段计数器的辅助部件和主要部件都必须更新。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式