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    • 1. 发明申请
    • SYSTEM AND METHOD FOR DYNAMIC MEMORY POWER MANAGEMENT
    • 动态记忆功率管理系统与方法
    • WO2014070264A1
    • 2014-05-08
    • PCT/US2013/051231
    • 2013-07-19
    • QUALCOMM INCORPORATED
    • LO, Haw-JingTAHA, AliCHUN, Dexter T.
    • G06F1/32
    • G06F1/3225G06F1/3275G06F12/023Y02D10/14Y02D50/20
    • Various embodiments of methods and systems for hardware (HW) based dynamic memory management in a portable computing device (PCD) are disclosed. One exemplary method includes generating a lookup table (LUT) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.
    • 公开了在便携式计算设备(PCD)中基于硬件(HW)的动态存储器管理的方法和系统的各种实施例。 一种示例性方法包括生成查找表(LUT)以跟踪位于易失性存储器的多个部分上的每个存储器页面。 更新LUT中的记录以跟踪数据位置。 当PCD进入睡眠状态以节省能量时,可以查询LUT以确定易失性存储器(例如,上部存储体)的第一部分中的哪些特定存储器页面包含数据内容以及易失性存储器的第二部分中的哪些页面 例如,较低的银行)可用于接收内容。 基于该查询,数据在上部存储器页面中的位置是已知的,并且可以被快速迁移到被识别用于接收数据的下部的存储器页面中。
    • 5. 发明申请
    • METHODS AND SYSTEMS FOR SMART REFRESH OF DYNAMIC RANDOM ACCESS MEMORY
    • 动态随机存取存储器的智能刷新方法与系统
    • WO2014186229A1
    • 2014-11-20
    • PCT/US2014/037525
    • 2014-05-09
    • QUALCOMM INCORPORATED
    • LO, Haw-JingCHUN, Dexter
    • G11C11/406G11C11/4072G11C7/04G06F13/16
    • G11C11/40622G11C7/04G11C11/40603G11C11/40611G11C11/40626G11C11/4072
    • Methods and devices for refreshing a dynamic memory device, (e.g., DRAM) to eliminate unnecessary page refresh operations. A value in a lookup table for the page may indicate whether valid data including all zeros is present in the page. When the page includes valid data of all zeros, the lookup table value may be set so that refresh, memory read, write and clear accesses of the page may be inhibited and a valid value may be returned. A second lookup table may contain a second value indicating whether a page has been accessed by a page read or write during the page refresh interval. A page refresh, by issuing an ACT -PRE command pair, and a page address may be performed according to the page refresh interval when the second value indicates that page access has not occurred.
    • 用于刷新动态存储设备(例如,DRAM)以消除不必要的页面刷新操作的方法和设备。 该页面的查找表中的值可以指示页面中是否存在包括全部零的有效数据。 当页面包括全零的有效数据时,可以设置查找表值,使得可以禁止页面的刷新,存储器读取,写入和清除访问,并且可以返回有效值。 第二查找表可以包含指示在页面刷新间隔期间页面是否被页面读取或写入访问的第二值。 当第二个值指示没有发生页面访问时,可以根据页面刷新间隔来执行通过发出ACT -PRE命令对的页面刷新和页面地址。
    • 7. 发明申请
    • SYSTEM AND METHOD FOR RESOLVING DRAM PAGE CONFLICTS BASED ON MEMORY ACCESS PATTERNS
    • 基于存储器访问模式解决DRAM页面冲突的系统和方法
    • WO2015106145A1
    • 2015-07-16
    • PCT/US2015/010883
    • 2015-01-09
    • QUALCOMM INCORPORATED
    • MONDAL, MrigankaLO, Haw-Jing
    • G11C11/4096G11C7/10
    • G06F3/0611G06F3/0655G06F3/0673G06F12/0607G06F13/1626G06F2212/652G11C7/1042G11C7/1072G11C7/1075G11C11/4096Y02D10/14
    • Systems, methods, and computer programs are disclosed for managing access requests to a DRAM memory device (104). One embodiment includes receiving memory access pattern data (116) for at least one of a plurality of memory clients (110) prior to a corresponding memory transaction with a DRAM memory device (104). Next, it is determined (114), based on the received memory access pattern data (116), that a future transaction of a first of the plurality of memory clients (110) may create a future page conflict with a current transaction of a second of the plurality of memory clients (110). The future page conflict is then resolved by interleaving access to an associated bank (106) in the DRAM memory device (104) by the first and second memory clients (110) according to the received memory access pattern data (116).
    • 公开了用于管理对DRAM存储器件(104)的访问请求的系统,方法和计算机程序。 一个实施例包括在与DRAM存储器设备(104)进行相应的存储器处理之前,为多个存储器客户端(110)中的至少一个接收存储器访问模式数据(116)。 接下来,基于所接收的存储器访问模式数据(116)确定(114)多个存储器客户端(110)中的第一个存储器客户端(110)的未来事务可能与第二个存储器访问模式数据 的多个存储器客户端(110)。 然后,根据接收到的存储器访问模式数据(116),通过第一和第二存储器客户端(110)对DRAM存储器设备(104)中的相关联存储体(106)的访问进行交织来解决未来页面冲突。
    • 10. 发明公开
    • METHOD AND APPARATUS FOR DRAM SPATIAL COALESCING WITHIN A SINGLE CHANNEL
    • VERFAHREN UND VORRICHTUNGFÜRRÄUMLICHEDRAM-KOALESZIERUNG IN EINEM EINZELKANAL
    • EP3087452A1
    • 2016-11-02
    • EP14825014.5
    • 2014-12-12
    • Qualcomm Incorporated
    • CHUN, Dexter TamioLO, Haw-JingDROP, Michael
    • G06F1/32G11C7/10
    • G06F12/06G06F1/3225G06F1/3275G06F13/1673Y02D10/13Y02D10/14Y02D50/20
    • Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.
    • 方面包括用于重新组织存储器中的数据存储器的计算设备,系统和方法,以激励小于用于读或写交易的存储器模块的所有存储器设备。 存储器件可以连接到单独的选择线,使得重新排序逻辑可以根据重新排序的存储器映射来确定存储器件激活事务。 重新排序逻辑可以重新排序存储器地址,使得由处理器为交易提供的存储器地址根据重新排序的存储器映射被转换为重新排序的存储器地址,而处理器不必改变其存储器地址方案。 重新排序的存储器映射可以提供由存储器件减少的能量消耗,或等待容忍过程的能量消耗和性能速度的平衡。