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    • 9. 发明申请
    • UNIVERSAL PROGRAMMABLE DELAY CELL
    • 通用可编程延迟电池
    • WO2003023581A2
    • 2003-03-20
    • PCT/US2002/028676
    • 2002-09-10
    • QUALCOMM INCORPORATED
    • KAZI, Tauseef
    • G06F1/10
    • G06F17/5045G06F1/10
    • A circuit and method for minimizing clock skew in an integrated circuit. The circuit is configured as a combination of delay elements and connection matrices that by connecting input and output pins in the connection matrix the circuit designer can select the required delay value. The connection matrices are defined in the circuit synthesis process as non routable areas therefore the programmable delay cells are programed after the circuit design is complete without requiring the circuit to be re routed. By inserting standard programmable delay cells in the clock tree the circuit designer can build in adjustable compensation for a wide range of clock skew.
    • 一种用于最小化集成电路中的时钟偏移的电路和方法。 该电路被配置为延迟元件和连接矩阵的组合,通过连接矩阵中的输入和输出引脚,电路设计者可以选择所需的延迟值。 连接矩阵在电路合成过程中被定义为不可路由的区域,因此可在电路设计完成之后对可编程延迟单元进行编程,而不需要重新路由电路。 通过在时钟树中插入标准可编程延迟单元,电路设计人员可以在宽范围的时钟偏移范围内构建可调补偿。