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1. 发明申请

WO2018004902A1 SYSTEM AND METHOD FOR ODD MODULUS MEMORY CHANNEL INTERLEAVING 审中-公开
标题翻译： ODD模存储器通道交织的系统和方法
公开(公告)号：WO2018004902A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/034587
申请日：2017-05-25
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio
IPC分类号： G06F12/06
摘要： A system for providing odd modulus memory channel interleaving may include a dynamic random access memory (DRAM) system and a system on chip (SoC). The SoC comprises a first memory controller, a second memory controller, and a symmetric memory channel interleaver. The first memory controller is electrically coupled to a first DRAM module via a first memory bus. The second memory controller is electrically coupled to a second DRAM module and a third DRAM module via a second memory bus. The symmetric memory channel interleaver is configured to uniformly distribute DRAM traffic to the first memory controller and the second memory controller. The first memory controller provides a first interleaved channel to the first DRAM module via the first memory bus. The second memory controller provides a second interleaved channel to the second DRAM module via upper address bits on the second memory bus.
摘要翻译：用于提供奇模数存储器通道交错的系统可以包括动态随机存取存储器（DRAM）系统和片上系统（SoC）。 SoC包括第一存储器控制器，第二存储器控制器和对称存储器信道交织器。第一存储器控制器经由第一存储器总线电耦合到第一DRAM模块。第二存储器控制器经由第二存储器总线电耦合到第二DRAM模块和第三DRAM模块。对称存储信道交织器被配置为将DRAM业务均匀地分配给第一存储器控制器和第二存储器控制器。第一存储器控制器经由第一存储器总线向第一DRAM模块提供第一交错信道。第二存储器控制器通过第二存储器总线上的高地址位向第二DRAM模块提供第二交错信道。

2. 发明申请

WO2017172268A1 POWER-REDUCING MEMORY SUBSYSTEM HAVING A SYSTEM CACHE AND LOCAL RESOURCE MANAGEMENT 审中-公开
公开(公告)号：WO2017172268A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/020811
申请日：2017-03-03
申请人： QUALCOMM INCORPORATED
发明人： LI, Yanru , CHUN, Dexter Tamio , ARTIERI, Alain
IPC分类号： G06F12/0862 , G06F1/32
摘要： Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

3. 发明申请

WO2017155662A1 MULTI-RANK COLLISION REDUCTION IN A HYBRID PARALLEL-SERIAL MEMORY SYSTEM 审中-公开
标题翻译：混合并行串行存储器系统中的多级降级
公开(公告)号：WO2017155662A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/017191
申请日：2017-02-09
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , LI, Yanru , JAFFARI, Javid , ANSARI, Amin
IPC分类号： G06F12/02 , G06F13/16 , G11C7/10 , G06F12/10 , G06F12/1081 , G06F12/08 , G06F12/06
摘要： Systems, methods, and computer programs are disclosed for allocating memory in a hybrid parallel/serial memory system. One method comprises configuring a memory address map for a multi-rank memory system with a dedicated serial access region in a first memory rank and a dedicated parallel access region in a second memory rank. A request is received for a virtual memory page. If the request comprises a performance hint, the virtual memory page is selectively assigned to a free physical page in the dedicated serial access in the first memory rank and the dedicated parallel access region in the second memory rank.
摘要翻译：公开了用于在混合并行/串行存储器系统中分配存储器的系统，方法和计算机程序。一种方法包括为具有第一存储器列中的专用串行存取区域和第二存储器列中的专用并行存取区域的多列存储器系统配置存储器地址映射。接收到虚拟内存页面的请求。如果请求包括性能提示，则将虚拟存储器页选择性地分配给第一存储器列中的专用串行访问中的空闲物理页面和第二存储器列中的专用并行访问区域。

4. 发明申请

WO2017105757A1 SYSTEMS, METHODS, AND COMPUTER PROGRAMS FOR RESOLVING DRAM DEFECTS 审中-公开
标题翻译：用于解决DRAM缺陷的系统，方法和计算机程序
公开(公告)号：WO2017105757A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/062574
申请日：2016-11-17
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , LI, Yanru
IPC分类号： G06F11/10
CPC分类号： G11C29/42 , G06F11/1016 , G06F11/1048 , G06F11/1064 , G06F11/1072 , G06F12/0246 , G06F12/0875 , G06F13/24 , G11C7/1072
摘要： Systems, methods, and computer programs are disclosed for resolving dynamic random access memory (DRAM) defects. One embodiment is a system comprising a dynamic random access memory (DRAM) system electrically coupled to a system on chip (SoC). The SoC comprises a cache and a cache controller. The cache controller is configured to store corrected data for a failed physical codeword address associated with the DRAM in the cache and provide further access to the failed physical codeword address from the cache instead of the DRAM system.
摘要翻译：公开了用于解决动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。一个实施例是包括电耦合到片上系统（SoC）的动态随机存取存储器（DRAM）系统的系统。 SoC包括缓存和缓存控制器。高速缓存控制器被配置为将关于DRAM中的失效物理码字地址的校正数据存储在高速缓存中，并且从高速缓存而不是DRAM系统提供对失效物理码字地址的进一步访问。

5. 发明申请

WO2017095592A1 SYSTEM AND METHOD FOR MEMORY MANAGEMENT USING DYNAMIC PARTIAL CHANNEL INTERLEAVING 审中-公开
标题翻译：使用动态部分通道交错的存储器管理系统和方法
公开(公告)号：WO2017095592A1
公开(公告)日：2017-06-08
申请号：PCT/US2016/060405
申请日：2016-11-03
申请人： QUALCOMM INCORPORATED
发明人： DE, Subrato , STEWART, Richard , CHUN, Dexter Tamio
IPC分类号： G06F12/06 , G06F12/10 , G06F12/1027
CPC分类号： G11C7/1072 , G06F3/061 , G06F3/0653 , G06F3/0685 , G06F12/0607 , G06F12/10 , G06F12/1027 , G06F13/1657 , G06F2212/657 , Y02D10/13 , Y02D10/14
摘要： Systems and methods are disclosed for providing memory channel interleaving with selective power/performance optimization. One such method comprises configuring an interleaved zone for relatively higher performance tasks, a linear address zone for relatively lower power tasks, and a mixed interleaved-linear zone for tasks with intermediate performance requirements. A boundary is defined among different zones using a sliding threshold address. The zones are dynamically adjusted, and/or new zones dynamically created, by changing the sliding address in real-time based on system goals and application performance preferences. A request for high performance memory is allocated to a zone with lower power that minimally supports the required performance, or may be allocated to a low power memory zone with lower than required performance if the system parameters indicate a need for aggressive power conservation. Pages may be migrated between zones in order to free a memory device for powering down.
摘要翻译：公开了用于提供具有选择性功率/性能优化的存储信道交织的系统和方法。一种这样的方法包括配置用于相对较高性能任务的交织区域，用于相对较低功率任务的线性地址区域以及用于具有中等性能要求的任务的混合交织线性区域。使用滑动阈值地址在不同区域之间定义边界。根据系统目标和应用程序性能偏好，通过实时更改滑动地址，动态调整区域和/或动态创建新区域。如果系统参数表明需要进行大量节能，则将对高性能内存的请求分配给功耗较低的区域，以最小程度地支持所需的性能，或者将其分配给低功耗内存区域，并且性能低于所需性能。页面可能会在区域之间迁移，以释放内存设备的电源。

6. 发明申请

WO2017083051A1 POWER-MINIMIZING VOLTAGE RAIL SELECTION IN A PORTABLE COMPUTING DEVICE 审中-公开
标题翻译：在便携式计算装置中的电力最小化电压轨选择
公开(公告)号：WO2017083051A1
公开(公告)日：2017-05-18
申请号：PCT/US2016/056888
申请日：2016-10-13
申请人： QUALCOMM INCORPORATED
发明人： STEWART, Richard , CHUN, Dexter Tamio , ARTIERI, Alain
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3287 , Y02D10/172 , Y02D50/20
摘要： Components of a portable computing device produce power supply voltage requests indicating requested power levels. In response to the power supply voltage requests, power multiplexers associated with the components select and couple corresponding voltage rails associated with two or more fixed-voltage power supplies to the requesting components. Power supplies may be activated and deactivated on an as-requested basis.
摘要翻译：便携式计算设备的组件产生指示所请求的功率水平的电源电压请求。响应于电源电压请求，与组件相关联的功率多路复用器选择并将与两个或更多个固定电压电源相关联的对应电压轨耦合到请求组件。电源可以根据要求启动和关闭。

7. 发明申请

WO2017074643A1 SYSTEM AND METHOD FOR FLASH READ CACHE WITH ADAPTIVE PRE-FETCH 审中-公开
标题翻译：具有自适应预取的闪存读取缓存的系统和方法
公开(公告)号：WO2017074643A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/054537
申请日：2016-09-29
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , LI, Yanru
IPC分类号： G06F12/02
CPC分类号： G06F12/0862 , G06F12/0246 , G06F12/0804 , G06F2212/1016 , G06F2212/6026 , G06F2212/7203
摘要： Systems and methods for improved flash memory performance in a portable computing device are presented. In a method, a value N corresponding to an amount of prefetch data to be retrieved from the flash memory is determined. An access request for a flash memory is received at a cache controller in communication with a cache memory. A determination is made whether the access request for the flash memory corresponds to a portion of data stored in the cache memory. If the access request for the flash memory corresponds to the portion of data, the portion of data is returned in response to the access request. Otherwise, an N amount of prefetch data is retrieved from the flash memory and stored in the cache memory. The value N is incremented based on a cache hit percentage for the cache memory.
摘要翻译：介绍了用于便携式计算设备中的改进闪存性能的系统和方法。在一种方法中，确定与从闪存中检索的预取数据量相对应的值N. 在与高速缓存存储器通信的高速缓存控制器处接收对闪存的访问请求。确定对闪存的访问请求是否对应于存储在高速缓冲存储器中的数据的一部分。如果闪存的访问请求对应于部分数据，则响应于访问请求返回部分数据。否则，从闪存中检索N个预取数据并将其存储在高速缓冲存储器中。值N是基于高速缓存存储器的高速缓存命中百分比递增的。

8. 发明申请

WO2016175959A1 METHODS AND APPARATUSES FOR MEMORY POWER REDUCTION 审中-公开
标题翻译：用于存储器功率降低的方法和装置
公开(公告)号：WO2016175959A1
公开(公告)日：2016-11-03
申请号：PCT/US2016/024569
申请日：2016-03-28
申请人： QUALCOMM INCORPORATED
发明人： TAHA, Ali , CHUN, Dexter Tamio
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3287 , G06F2212/1028 , G06F2212/205 , G11C11/406 , G11C14/0009 , G11C14/0054 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatuses for memory power reduction are provided. The apparatus determines whether to store data into a DRAM or an NVRAM during an idle state of a processor based on power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by the processor, based on power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data. The NVRAM is a type of non-volatile random-access memory other than flash memory. The processor stores the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.
摘要翻译：提供了用于存储器功率降低的方法和装置。该设备基于DRAM的功耗与DRAM中的数据相关联以及处理器中存储在DRAM中的数据的使用，确定在处理器的空闲状态期间是否将数据存储到DRAM或NVRAM中关于由处理器使用存储在NVRAM中的数据以及与数据相关联的与第一功率状态和第二功率状态相关联的电流相关联的占空比，NVRAM的功耗。 NVRAM是除闪存之外的一种非易失性随机存取存储器。根据是否将数据存储在DRAM或NVRAM中，处理器将数据存储到DRAM或NVRAM中的一个中。

9. 发明申请

WO2016168602A2 SYSTEMS AND METHODS TO REFRESH DRAM 审中-公开
标题翻译：重构DRAM的系统和方法
公开(公告)号：WO2016168602A2
公开(公告)日：2016-10-20
申请号：PCT/US2016/027761
申请日：2016-04-15
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , KIM, Jung Pill , LI, Yanru
IPC分类号： G11C11/406 , G11C29/02 , G11C29/50
CPC分类号： G11C11/40626 , G11C7/1006 , G11C11/4076 , G11C11/4096 , G11C29/023 , G11C29/028 , G11C29/36 , G11C29/42 , G11C29/50016 , G11C2207/2245 , G11C2211/4062
摘要： A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.
摘要翻译：公开了一种刷新动态随机存取存储器（DRAM）的系统和方法。一种器件包括通过总线耦合到DRAM的DRAM，总线和片上系统（SOC）。 SOC被配置为基于DRAM的温度以基于在SOC耦合到DRAM时执行的一个或多个校准测试确定的校准数据以特定刷新速率刷新DRAM。

10. 发明申请

WO2015100038A1 METHOD AND APPARATUS FOR DRAM SPATIAL COALESCING WITHIN A SINGLE CHANNEL 审中-公开
标题翻译：用于单个通道中的DRAM空间分析的方法和装置
公开(公告)号：WO2015100038A1
公开(公告)日：2015-07-02
申请号：PCT/US2014/070123
申请日：2014-12-12
申请人： QUALCOMM INCORPORATED
发明人： CHUN, Dexter Tamio , LO, Haw-Jing , DROP, Michael
IPC分类号： G06F1/32 , G11C7/10
CPC分类号： G06F12/06 , G06F1/3225 , G06F1/3275 , G06F13/1673 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.
摘要翻译：方面包括用于重新组织存储器中的数据存储器的计算设备，系统和方法，以激励小于用于读取或写入事务的存储器模块的所有存储器设备。存储器件可以连接到单独的选择线，使得重新排序逻辑可以根据重新排序的存储器映射来确定存储器件激活事务。重新排序逻辑可以重新排序存储器地址，使得由处理器为交易提供的存储器地址根据重新排序的存储器映射被转换为重新排序的存储器地址，而处理器不必改变其存储器地址方案。重新排序的存储器映射可以提供由存储器件减少的能量消耗，或等待容忍过程的能量消耗和性能速度的平衡。

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