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1. 发明申请

US20130078773A1 Method for manufacturing CMOS FET 有权
公开(公告)号：US20130078773A1
公开(公告)日：2013-03-28
申请号：US13576658
申请日：2011-11-22
申请人： Qiuxia Xu , Yongliang Li , Gaobo Xu
发明人： Qiuxia Xu , Yongliang Li , Gaobo Xu
IPC分类号： H01L21/8238
CPC分类号： H01L21/8238 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate. The first hard mask and the second hard mask are removed by etching; a polysilicon layer and a third hard mask are deposited and patterned by lithography and etching to form a gate stack; a dielectric layer is deposited and etched to form first spacers. Source/drain regions and their extensions are then formed by a conventional process, and silicides are formed by silicidation to provide contact and metallization.

2. 发明授权

US08530302B2 Method for manufacturing CMOS FET 有权
标题翻译：制造CMOS FET的方法
公开(公告)号：US08530302B2
公开(公告)日：2013-09-10
申请号：US13576658
申请日：2011-11-22
申请人： Qiuxia Xu , Yongliang Li , Gaobo Xu
发明人： Qiuxia Xu , Yongliang Li , Gaobo Xu
IPC分类号： H01L21/8238 , H01L21/4763
CPC分类号： H01L21/8238 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate. The first hard mask and the second hard mask are removed by etching; a polysilicon layer and a third hard mask are deposited and patterned by lithography and etching to form a gate stack; a dielectric layer is deposited and etched to form first spacers. Source/drain regions and their extensions are then formed by a conventional process, and silicides are formed by silicidation to provide contact and metallization.
摘要翻译：制造CMOS FET的方法包括在形成常规介电隔离之后在半导体衬底上形成第一界面SiO 2层; 形成堆叠第一高K栅极电介质/第一金属栅极; 沉积第一个硬掩模; 通过光刻和蚀刻图案化第一硬掩模; 蚀刻未被第一硬掩模覆盖的第一金属栅极和第一高K栅极电介质的部分。然后形成第二界面SiO 2层和第二高K栅极电介质/第二金属栅极的叠层; 通过光刻和蚀刻沉积和图案化第二个硬掩模; 蚀刻未被第二硬掩模覆盖的第二金属栅极和第二高K栅极电介质的部分以露出第一金属栅极上的第一硬掩模。通过蚀刻去除第一硬掩模和第二硬掩模; 通过光刻和蚀刻沉积多晶硅层和第三硬掩模并图案化以形成栅叠层; 沉积和蚀刻电介质层以形成第一间隔物。然后通过常规工艺形成源极/漏极区及其延伸，并且通过硅化物形成硅化物以提供接触和金属化。

3. 发明申请

US20130130448A1 METHOD FOR FORMING AND CONTROLLING MOLECULAR LEVEL SiO2 INTERFACE LAYER 有权
标题翻译：用于形成和控制分子级SiO2界面层的方法
公开(公告)号：US20130130448A1
公开(公告)日：2013-05-23
申请号：US13502788
申请日：2012-02-28
申请人： Qiuxia Xu , Gaobo Xu
发明人： Qiuxia Xu , Gaobo Xu
IPC分类号： H01L21/8238
CPC分类号： H01L29/511 , H01L21/02057 , H01L21/02164 , H01L21/02238 , H01L21/02255 , H01L21/28088 , H01L21/28185 , H01L21/28202 , H01L21/823857 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： The present disclosure provides a method for forming and controlling a molecular level SiO2 interface layer, mainly comprising: cleansing before growing the SiO2 interface layer, growing the molecular level ultra-thin SiO2 interface layer; and controlling reaction between high-K gate dielectric and the SiO2 interface layer to further reduce the SiO2 interface layer. The present disclosure can strictly prevent invasion of oxygen during process integration. The present disclosure can obtain a good-quality high-K dielectric film having a small EOT. The manufacturing process is simple and easy to integrate. It is also compatible with planar CMOS process, and can satisfy requirement of high-performance nanometer level CMOS metal gate/high-K device of 45 nm node and below.
摘要翻译：本发明提供了一种用于形成和控制分子水平SiO 2界面层的方法，主要包括：在生长SiO 2界面层之前进行清洗，生长分子级超薄SiO 2界面层; 并控制高K栅极电介质和SiO 2界面层之间的反应，以进一步降低SiO 2界面层。本公开可以严格地防止过程整合期间的氧侵入。本公开可以获得具有小EOT的优质高K电介质膜。制造过程简单易于集成。它还兼容平面CMOS工艺，可以满足45纳米以下节点的高性能纳米级CMOS金属栅极/高K器件的要求。

4. 发明申请

US20130005097A1 METHOD FOR INTEGRATING REPLACEMENT GATE IN SEMICONDUCTOR DEVICE 有权
标题翻译：用于在半导体器件中集成更换栅的方法
公开(公告)号：US20130005097A1
公开(公告)日：2013-01-03
申请号：US13379169
申请日：2011-08-02
申请人： Gaobo Xu , Qiuxia Xu
发明人： Gaobo Xu , Qiuxia Xu
IPC分类号： H01L21/8238 , H01L21/336 , B82Y40/00
CPC分类号： H01L29/66545 , H01L21/823842
摘要： A method for integrating a replacement gate in a semiconductor device is disclosed. The method may comprise: forming a well region on a semiconductor substrate, and defining a N-type device region and/or a P-type device region; forming a sacrificial gate stack or sacrificial gate stacks respectively on the N-type device region and/or the P-type device region, the sacrificial gate stack or each of the sacrificial gate stacks comprising a sacrificial gate dielectric layer and a sacrificial gate electrode layer, wherein the sacrificial gate dielectric layer is disposed on the semiconductor substrate, and the sacrificial gate electrode layer is disposed on the sacrificial gate dielectric layer; forming a spacer or spacers surrounding the sacrificial gate stack or the respective sacrificial gate stacks; forming source/drain regions on both sides of the sacrificial gate stack or the respective sacrificial gate stacks and embedded into the semiconductor substrate; forming a SiO2 layer on the semiconductor substrate; forming a SOG layer on the SiO2 layer; etching the SOG layer until the SiO2 layer is exposed; etching the SOG layer and the SiO2 layer at different rates in such a manner that the SiO2 layer is planarized; and forming a N-type replacement gate stack on the N-type device region and/or a P-type replacement gate stack on the P-type device region, respectively.
摘要翻译：公开了一种在半导体器件中集成置换栅极的方法。该方法可以包括：在半导体衬底上形成阱区，并且限定N型器件区和/或P型器件区; 在N型器件区域和/或P型器件区域上分别形成牺牲栅极堆叠或牺牲栅极堆叠，牺牲栅极堆叠或每个牺牲栅极堆叠包括牺牲栅极电介质层和牺牲栅极电极层其中所述牺牲栅极电介质层设置在所述半导体衬底上，并且所述牺牲栅极电极层设置在所述牺牲栅极电介质层上; 形成围绕所述牺牲栅极叠层或相应的牺牲栅极叠层的间隔物或间隔物; 在牺牲栅极堆叠或相应的牺牲栅极堆叠的两侧上形成源极/漏极区域并嵌入到半导体衬底中; 在所述半导体衬底上形成SiO 2层; 在SiO 2层上形成SOG层; 蚀刻SOG层直到暴露SiO 2层; 以使SiO 2层平坦化的方式以不同的速率蚀刻SOG层和SiO 2层; 以及分别在P型器件区域上的N型器件区域和/或P型替换栅极堆叠上形成N型替换栅极堆叠。

5. 发明申请

US20110256701A1 METHOD FOR TUNING THE WORK FUNCTION OF A METAL GATE OF THE PMOS DEVICE 有权
标题翻译：用于调谐PMOS器件的金属栅的工作功能的方法
公开(公告)号：US20110256701A1
公开(公告)日：2011-10-20
申请号：US12990735
申请日：2010-06-28
申请人： Qiuxia Xu , Gaobo Xu
发明人： Qiuxia Xu , Gaobo Xu
IPC分类号： H01L21/28
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28176 , H01L21/28202 , H01L21/32136 , H01L21/3215 , H01L21/823828 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： The present application discloses a method for tuning the work function of a metal gate of the PMOS device, comprising the steps of depositing a layer of metal nitride or a metal on a layer of high-k gate dielectric by physical vapor deposition (PVD), as a metal gate; doping the metal gate with dopants such as Al, Pt, Ru, Ga, Ir by ion implantation; and driving the doped metal ions to the interface between the high-k gate dielectric and interfacial SiO2 by high-temperature annealing so that the doped metal ions accumulate at the interface or generate dipoles by interfacial reaction, which in turn tunes the work function of the metal gate. The inventive method can be widely used and its process is simple and convenient, has a better ability of tuning the work function of the metal gate, and is compatible with the conventional CMOS process.
摘要翻译：本申请公开了一种用于调谐PMOS器件的金属栅极的功函数的方法，包括以下步骤：通过物理气相沉积（PVD）将金属氮化物或金属层沉积在高k栅极电介质层上，作为金属门; 通过离子注入对诸如Al，Pt，Ru，Ga，Ir的掺杂剂掺杂金属栅; 并通过高温退火将掺杂的金属离子驱动到高k栅极电介质和界面SiO 2之间的界面，使得掺杂的金属离子在界面处积累或通过界面反应产生偶极子，这进而调节了金属门。本发明的方法可以广泛使用，其工艺简单方便，具有更好的调谐金属栅极功能的能力，并且与传统的CMOS工艺兼容。

6. 发明申请

US20150170974A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150170974A1
公开(公告)日：2015-06-18
申请号：US14355919
申请日：2012-12-07
申请人： Qiuxia Xu , Huilong Zhu , Gaobo Xu , Huajie Zhou , Dapeng Chen
发明人： Qiuxia Xu , Huilong Zhu , Gaobo Xu , Huajie Zhou , Dapeng Chen
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/3105 , H01L21/321 , H01L21/324 , H01L29/167 , H01L21/266 , H01L29/66 , H01L29/51 , H01L29/423 , H01L29/49 , H01L21/3213 , H01L21/02
CPC分类号： H01L21/823857 , H01L21/0228 , H01L21/0254 , H01L21/266 , H01L21/28141 , H01L21/28176 , H01L21/31051 , H01L21/3212 , H01L21/3213 , H01L21/324 , H01L21/823842 , H01L29/167 , H01L29/42364 , H01L29/42372 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse and accumulate at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide layer, and electric dipoles are generated by interfacial reaction at the lower interface between the high-K gate dielectric and the interfacial oxide layer.
摘要翻译：一种制造半导体器件的方法，包括：在所述半导体衬底上限定有源区; 在所述半导体衬底的表面上形成界面氧化物层; 在界面氧化物层上形成高K栅电介质; 在高K栅极电介质上形成第一金属栅极层; 在所述第一金属栅极层上形成伪栅极层; 图案化虚拟栅极层，第一金属栅极层，高K栅极电介质和界面氧化物层以形成栅极堆叠结构; 形成围绕所述栅堆叠结构的栅极间隔; 分别形成NMOS和PMOS的S / D区域; 通过CMP沉积层间电介质和平面化以暴露虚拟栅极层的表面; 去除虚拟栅极层以形成栅极开口; 将掺杂剂离子注入到第一金属栅极层中; 在所述第一金属栅极层上形成第二金属栅极层以填充所述栅极开口; 并执行退火，使得掺杂剂离子在高K栅极电介质和第一金属栅极层之间以及高K栅极电介质和界面氧化物层之间的下界面处的上界面处扩散并积聚，并且电偶极子通过界面反应在高K栅极电介质和界面氧化物层之间的下界面产生。

7. 发明申请

US20120164808A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120164808A1
公开(公告)日：2012-06-28
申请号：US13129419
申请日：2011-02-17
申请人： Huaxiang Yin , Qiuxia Xu , Gaobo Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Gaobo Xu , Lingkuan Meng , Tao Yang , Dapeng Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/823842 , H01L21/31055 , H01L21/31116 , H01L21/76819 , H01L29/66545 , H01L29/78
摘要： A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

8. 发明授权

US09049061B2 CMOS device and method for manufacturing the same 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US09049061B2
公开(公告)日：2015-06-02
申请号：US13640733
申请日：2012-04-11
申请人： Qiuxia Xu , Chao Zhao , Gaobo Xu
发明人： Qiuxia Xu , Chao Zhao , Gaobo Xu
IPC分类号： H01L27/092 , H01L21/265 , H04L21/02
CPC分类号： H04L21/02 , H01L21/265 , H01L21/823807 , H01L29/7833 , H01L29/7843
摘要： This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.
摘要翻译：本发明公开了一种CMOS器件，其包括：第一MOSFET; 与第一MOSFET的类型不同的第二MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力层; 以及覆盖所述第二MOSFET的第二应力层，其中所述第二应力层掺杂有离子，并且因此具有不同于所述第一应力的第二应力。本发明的CMOS器件及其制造方法利用分离离子注入方法实现双重应力衬垫，而不需要通过光刻/光刻技术去除PMOS区域上的拉伸应力层或NMOS区域上的压应力层，蚀刻，从而简化了工艺并降低了成本，并且同时防止了NMOS区域或PMOS区域上的衬垫中的应力不受由沉积工艺的热处理引起的损伤。

9. 发明授权

US08822292B2 Method for forming and controlling molecular level SiO2 interface layer 有权
标题翻译：分子级SiO2界面层的形成和控制方法
公开(公告)号：US08822292B2
公开(公告)日：2014-09-02
申请号：US13502788
申请日：2012-02-28
申请人： Qiuxia Xu , Gaobo Xu
发明人： Qiuxia Xu , Gaobo Xu
IPC分类号： H01L21/336 , H01L29/51
CPC分类号： H01L29/511 , H01L21/02057 , H01L21/02164 , H01L21/02238 , H01L21/02255 , H01L21/28088 , H01L21/28185 , H01L21/28202 , H01L21/823857 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： The present disclosure provides a method for forming and controlling a molecular level SiO2 interface layer, mainly comprising: cleansing before growing the SiO2 interface layer, growing the molecular level ultra-thin SiO2 interface layer; and controlling reaction between high-K gate dielectric and the SiO2 interface layer to further reduce the SiO2 interface layer. The present disclosure can strictly prevent invasion of oxygen during process integration. The present disclosure can obtain a good-quality high-K dielectric film having a small EOT. The manufacturing process is simple and easy to integrate. It is also compatible with planar CMOS process, and can satisfy requirement of high-performance nanometer level CMOS metal gate/high-K device of 45 nm node and below.
摘要翻译：本发明提供了一种用于形成和控制分子水平SiO 2界面层的方法，主要包括：在生长SiO 2界面层之前进行清洗，生长分子级超薄SiO 2界面层; 并控制高K栅极电介质和SiO 2界面层之间的反应，以进一步降低SiO 2界面层。本公开可以严格地防止过程整合期间的氧侵入。本公开可以获得具有小EOT的优质高K电介质膜。制造过程简单易于集成。它还兼容平面CMOS工艺，可以满足45纳米以下节点的高性能纳米级CMOS金属栅极/高K器件的要求。

10. 发明申请

US20130099328A1 P-TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： P型半导体器件及其制造方法
公开(公告)号：US20130099328A1
公开(公告)日：2013-04-25
申请号：US13125710
申请日：2011-02-27
申请人： Gaobo Xu , Qiuxia Xu
发明人： Gaobo Xu , Qiuxia Xu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L29/51 , H01L29/513 , H01L29/66477 , H01L29/66575 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET.
摘要翻译：本申请提供了一种p型半导体器件及其制造方法。该器件的结构包括：半导体衬底; 位于半导体衬底中的沟道区; 栅极堆叠，其位于包括栅极介电层和栅电极的沟道区上，其中所述栅极介电层位于所述沟道区上，并且所述栅电极位于所述栅极电介质层上; 以及源极/漏极区域，位于沟道区域的两侧并嵌入到半导体衬底中; 其中元件Al分布在栅极电介质层的上表面，底表面和栅电极的底表面中的至少一个中。本发明的实施例可用于制造MOSFET。

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