专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06184061B2 Electrode of semiconductor device, method of manufacturing thereof, and the semicondutor device 失效
标题翻译：半导体装置的电极，其制造方法以及半导体装置
公开(公告)号：US06184061B2
公开(公告)日：2001-02-06
申请号：US09166908
申请日：1998-10-06
申请人： Qiang Wu , Yoshihiro Tomita
发明人： Qiang Wu , Yoshihiro Tomita
IPC分类号： H01L2128
CPC分类号： H05K3/244 , H01L21/4853 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05571 , H01L2224/13023 , H01L2224/13099 , H01L2224/16225 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/15311 , H01L2924/19041 , H01L2924/19043
摘要： An electrode of a semiconductor device comprising: a pad; an electroless diffusion prevention film formed on a surface of the pad for preventing material of the pad from diffusing; a solder precoat film formed on a surface of the electroless diffusion prevention film, and having a thickness not larger than a predetermined value, for preventing a solder bump on the solder precoat film from defective breaking; and a predetermined intermetallic compound layer formed in the solder precoat film in the vicinity of a boundary surface between the solder precoat film and the electroless diffusion prevention film, the intermetallic compound layer having a bonded surface bonded substantially to the whole of the surface of the electroless diffusion prevention film.
摘要翻译：一种半导体器件的电极，包括：衬垫; 形成在所述垫的表面上用于防止所述垫的材料扩散的无电扩散防止膜; 形成在无电扩散防止膜的表面上并且具有不大于预定值的厚度的焊料预涂膜，用于防止焊料预涂膜上的焊料凸起不良断裂; 以及形成在焊料预涂层中的预定的金属间化合物层，其在焊料预涂膜和无电扩散防止膜之间的边界面附近，具有接合表面的金属间化合物层基本上与化学镀的整个表面结合防扩散膜。

2. 发明授权

US06259161B1 Circuit electrode connected to a pattern formed on an organic substrate and method of forming the same 失效
标题翻译：连接到有机基板上形成的图案的电路电极及其形成方法
公开(公告)号：US06259161B1
公开(公告)日：2001-07-10
申请号：US09444825
申请日：1999-11-22
申请人： Qiang Wu , Yoshihiro Tomita
发明人： Qiang Wu , Yoshihiro Tomita
IPC分类号： H01L2348
CPC分类号： H05K3/244 , H01L23/49811 , H01L2924/0002 , H01L2924/00
摘要： There is described a circuit electrode formed in an integrated circuit package, which imparts sufficient bonding strength to a soldered section and prevents oxidation of the surface of an Ni—P film without fail. A circuit electrode to be electrically connected to a pattern formed on an organic substrate is formed. An electroless high-concentration Ni—P plating film containing phosphorous at a concentration of 7 to 12 wt. % is formed to a thickness of 3 to 10 &mgr;m so as to cover predetermined portions of the pattern. An electroless low-concentration Ni—P plating film containing phosphorous at a concentration of 3 wt. % or less is formed to a thickness of 0.5 to 10 &mgr;m so as to cover the electroless high-concentration Ni—P plating film. An electroless gold plating film is formed, as an oxidation prevention film, to a thickness of 0.05 to 0.5 &mgr;m so as to cover the surface of the electroless low-concentration Ni—P plating film.
摘要翻译：描述了一种形成在集成电路封装中的电路电极，其赋予焊接部分足够的接合强度，并且防止Ni-P膜的表面的氧化没有失败。形成与形成在有机基板上的图案电连接的电路电极。含有浓度为7〜12重量％的磷的无电解高浓度Ni-P镀膜。％形成为3〜10μm的厚度，以覆盖图案的预定部分。含有浓度为3重量％的磷的无电解低浓度Ni-P镀膜％以下的厚度形成为0.5〜10μm的厚度，以覆盖无电解高浓度Ni-P镀膜。作为防氧化膜形成厚度为0.05〜0.5μm的无电镀金膜，以覆盖无电解低浓度Ni-P镀膜的表面。

3. 发明申请

US20190099776A1 COMPRESSIBLE MEDIA APPLICATOR, APPLICATION SYSTEM AND METHODS FOR SAME 审中-公开
公开(公告)号：US20190099776A1
公开(公告)日：2019-04-04
申请号：US15720497
申请日：2017-09-29
申请人： Ken P. Hackenberg , Nachiket R. Raravikar , James C. Matayabas, JR. , Elizabeth Nofen , Nisha Ananthakrishnan , Manabu Nakagawasai , Yoshihiro Tomita
发明人： Ken P. Hackenberg , Nachiket R. Raravikar , James C. Matayabas, JR. , Elizabeth Nofen , Nisha Ananthakrishnan , Manabu Nakagawasai , Yoshihiro Tomita
IPC分类号： B05C5/02 , F16K21/18 , B05B1/02 , B05B1/30
摘要： A fluid applicator configured to apply a fluid to at least one substrate feature. The includes compressible reticulated media including an input interface configured for coupling with a fluid reservoir, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the applicator profile. The compressible reticulated media includes filling and dispensing configurations. In the dispensing configuration the substrate interface is configured for engagement with the at least one substrate feature, the compressible reticulated media is compressed, and according to the compression the fluid is applied across the feature profile. In the filling configuration the compressible reticulated media is configured for expansion relative to the dispensing configuration, and the fluid infiltrates the reticulations according to the expansion.

4. 发明申请

US20150270169A1 METHODS OF CONNECTING A FIRST ELECTRONIC PACKAGE TO A SECOND ELECTRONIC PACKAGE 有权
标题翻译：将第一电子包连接到第二电子包的方法
公开(公告)号：US20150270169A1
公开(公告)日：2015-09-24
申请号：US14219749
申请日：2014-03-19
申请人： Chia-Pin Chiu , Kinya Ichikawa , Yoshihiro Tomita , Robert L. Sankman , Eric Li
发明人： Chia-Pin Chiu , Kinya Ichikawa , Yoshihiro Tomita , Robert L. Sankman , Eric Li
IPC分类号： H01L21/768 , H01L21/56 , H01L23/00 , H01L25/00 , H01L25/065
CPC分类号： H01L25/50 , H01L21/4853 , H01L21/565 , H01L23/3121 , H01L23/49811 , H01L24/03 , H01L24/11 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2224/16227 , H01L2224/48227 , H01L2224/81801 , H01L2225/06517 , H01L2225/06548 , H01L2225/06555 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2924/01029 , H01L2924/06 , H01L2924/15311 , H01L2924/15321 , H01L2924/1815 , H01L2924/381
摘要： A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects.
摘要翻译：一种制造电子封装的方法。该方法包括用电导体填充模具以在模具内形成多个电互连。模具包括填充有多个电导体以形成多个电互连的开口。制造电子封装的方法还包括将模具附接到基板，使得电互连件接合基板上的电触点。制造电子封装的方法还可以包括在电绝缘体上形成接合电互连并将管芯连接到衬底上的导电焊盘，使得管芯电连接到至少一些电互连。

5. 发明申请

US20130122656A1 FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE 有权
标题翻译：半导体封装上的柔性互连图案
公开(公告)号：US20130122656A1
公开(公告)日：2013-05-16
申请号：US13734861
申请日：2013-01-04
申请人： Yoshihiro Tomita , David Chau , Gregory M. Chrysler , Devendra Natekar
发明人： Yoshihiro Tomita , David Chau , Gregory M. Chrysler , Devendra Natekar
IPC分类号： H01L21/768
CPC分类号： H01L21/4867 , H01L21/563 , H01L23/3675 , H01L23/42 , H01L23/5389 , H01L24/24 , H01L2223/6677 , H01L2224/16225 , H01L2224/18 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/73259 , H01L2224/73267 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/1423 , H01L2924/15311 , H01L2924/16152 , H01L2924/351 , H01L2924/00
摘要： An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
摘要翻译：本发明的一个实施例是制造金属互连的技术。将第一金属迹线印刷在附接到封装中的散热器的基板或空腔的管芯上，以将第一金属迹线电连接到基板中的电源触点。设备安装在第一个金属轨迹上。当封装电源时，该设备从基板接收电力。

6. 发明授权

US08387240B2 Methods for making multi-chip packaging using an interposer 有权
标题翻译：使用插入片进行多芯片封装的方法
公开(公告)号：US08387240B2
公开(公告)日：2013-03-05
申请号：US12955816
申请日：2010-11-29
申请人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
发明人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
IPC分类号： H01K3/10
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L25/0655 , H01L2224/81203 , H01L2224/81815 , H01L2924/10253 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49163 , Y10T29/49165 , H01L2924/00
摘要： In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.
摘要翻译：在一个实施例中，一种方法包括通过主体部分地形成多个通孔，通孔包括由身体限定的侧壁。电绝缘层形成在主体的侧壁和上表面上。在通孔和上表面上的绝缘层上形成导电层，导电层限定上表面上的第一金属焊盘和与第一金属焊盘接触的第二金属焊盘，第二金属焊盘具有较密的间距比第一金属垫。在相邻的第一金属焊盘之间和相邻的第二金属焊盘之间形成介电层。身体通过下表面变薄，并且通孔中的电绝缘层被暴露。在变薄之后，去除通孔中的电绝缘层的一部分。主体耦合到基板。

7. 发明授权

US08354748B2 In-package microelectronic apparatus, and methods of using same 有权
标题翻译：包装内微电子装置及其使用方法
公开(公告)号：US08354748B2
公开(公告)日：2013-01-15
申请号：US13354708
申请日：2012-01-20
申请人： Sriram Dattaguru , Lesley A. Polka Wood , Yoshihiro Tomita , Kiniya Ichikawa , Robert L. Sankman
发明人： Sriram Dattaguru , Lesley A. Polka Wood , Yoshihiro Tomita , Kiniya Ichikawa , Robert L. Sankman
IPC分类号： H01L23/34 , H01L21/00 , H05K1/18
CPC分类号： H01L25/0657 , H01L23/5384 , H01L23/5389 , H01L24/48 , H01L24/82 , H01L25/18 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/06517 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01065 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.
摘要翻译：用于处理器的安装基板包括裸片侧和在裸片侧配置有处理器占位面的平台侧。处理器占用面积耦合到至少一个处理器互连，并且微电子管芯嵌入在安装衬底中。微电子管芯耦合到处理器互连，并且待处理器占用的处理器之间的通信速率在10Gb / s至1Tb / s之间。

8. 发明申请

US20120289002A1 FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE 有权
标题翻译：半导体封装上的柔性互连图案
公开(公告)号：US20120289002A1
公开(公告)日：2012-11-15
申请号：US13556079
申请日：2012-07-23
申请人： Yoshihiro Tomita , David Chau , Gregory M. Chrysler , Devendra Natekar
发明人： Yoshihiro Tomita , David Chau , Gregory M. Chrysler , Devendra Natekar
IPC分类号： H01L21/50
CPC分类号： H01L21/4867 , H01L21/563 , H01L23/3675 , H01L23/42 , H01L23/5389 , H01L24/24 , H01L2223/6677 , H01L2224/16225 , H01L2224/18 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/73259 , H01L2224/73267 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/1423 , H01L2924/15311 , H01L2924/16152 , H01L2924/351 , H01L2924/00
摘要： An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
摘要翻译：本发明的一个实施例是制造金属互连的技术。将第一金属迹线印刷在附接到封装中的散热器的基板或空腔的管芯上，以将第一金属迹线电连接到基板中的电源触点。设备安装在第一个金属轨迹上。当封装电源时，该设备从基板接收电力。

9. 发明申请

US20120038033A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120038033A1
公开(公告)日：2012-02-16
申请号：US13285896
申请日：2011-10-31
申请人： Akira OGA , Yoshihiro Tomita , Masanori Minamio
发明人： Akira OGA , Yoshihiro Tomita , Masanori Minamio
IPC分类号： H01L23/495
CPC分类号： H01L21/565 , H01L23/3107 , H01L23/4334 , H01L23/49537 , H01L23/49562 , H01L23/49568 , H01L23/49575 , H01L23/552 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48137 , H01L2224/48247 , H01L2224/4903 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01013 , H01L2924/01028 , H01L2924/01047 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00 , H01L2224/45147 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012 , H01L2924/206
摘要： A semiconductor device includes a first semiconductor chip 1, a second semiconductor chip 4, a first lead frame 3 including a first die pad 9 on which the first semiconductor chip 1 is mounted, and a second lead frame 5 including a second die pad 11 on which the second semiconductor chip 4 is mounted. A sealing structure 6 covers the first semiconductor chip 1 and the second semiconductor chip 4. A noise shield 7 is disposed between the first semiconductor chip 1 and the second semiconductor chip 4.
摘要翻译：半导体器件包括第一半导体芯片1，第二半导体芯片4，第一引线框架3，第一引线框架3和第二引线框架3，第一引线框架3包括安装有第一半导体芯片1的第一管芯焊盘9和第二引线框架5，第二半导体芯片4被安装。密封结构6覆盖第一半导体芯片1和第二半导体芯片4.噪声屏蔽7设置在第一半导体芯片1和第二半导体芯片4之间。

10. 发明申请

US20110147905A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147905A1
公开(公告)日：2011-06-23
申请号：US13039937
申请日：2011-03-03
申请人： Masaki Utsumi , Hikari Sano , Hiroaki Fujimoto , Yoshihiro Tomita
发明人： Masaki Utsumi , Hikari Sano , Hiroaki Fujimoto , Yoshihiro Tomita
IPC分类号： H01L23/06 , H01L21/78
CPC分类号： H01L33/62 , H01L21/76898 , H01L23/481 , H01L27/14618 , H01L2224/0554 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/13025 , H01L2224/16225 , H01L2924/00014 , H01L2924/01055 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： In a semiconductor element, upper through-hole conductor portions and lower through-hole conductor portions are formed such that pore size A of the joint surface of the upper through-hole conductor portion and the lower through-hole conductor portion is smaller than pore size B of the upper through-hole conductor portion on the major surface of the semiconductor element and pore size C of the lower through-hole conductor portion on the other surface of the semiconductor element. Further, electrode portions are formed respectively on the top surfaces of the upper through-hole conductor portions and protrusions 4 are formed respectively on the top surfaces of the electrode portions. Moreover, an optical member pressed in contact with the protrusions is fixed on the semiconductor element with an adhesive.
摘要翻译：在半导体元件中，形成上通孔导体部和下通孔导体部，使得上通孔导体部和下通孔导体部的接合面的孔径A小于孔径 B，半导体元件的主表面上的上通孔导体部分的孔径C和半导体元件另一表面上的下通孔导体部分的孔径C. 此外，电极部分分别形成在上通孔导体部分的顶表面上，突起4分别形成在电极部分的顶表面上。此外，用粘合剂固定在半导体元件上与突起接触的光学部件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式