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1. 发明申请

WO2012125767A1 CHARGE PUMP ELECTROSTATIC DISCHARGE PROTECTION 审中-公开
标题翻译：充电泵静电放电保护
公开(公告)号：WO2012125767A1
公开(公告)日：2012-09-20
申请号：PCT/US2012/029129
申请日：2012-03-14
申请人： QUALCOMM INCORPORATED , SRIVASTAVA, Ankit , WORLEY, Eugene, R. , MIAO, Guoqing , QUAN, Xiaohong
发明人： SRIVASTAVA, Ankit , WORLEY, Eugene, R. , MIAO, Guoqing , QUAN, Xiaohong
IPC分类号： H03F1/52 , H01L27/02 , H02M3/07
CPC分类号： H03F1/52 , H01L27/0285 , H02M1/32 , H02M3/07
摘要： Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.
摘要翻译：用于放大器和使用电荷泵的其他电路的静电放电（ESD）保护技术。在示例性实施例中，响应于在电源电压节点和负输出电压节点之间检测到ESD事件，将第二飞跨电容器节点耦合到负输出电压节点的Vneg开关闭合。响应于在接地节点和负输出电压节点之间检测到ESD事件，将接地节点耦合到第二飞跨电容器节点的接地开关闭合。响应于在接地节点和负输出电压节点之间检测到ESD事件，Vneg开关进一步闭合。公开了用于在耦合到电荷泵的功率放大器的输出处提供片上快速恢复钳位以防止由标准IEC 61000-4-2定义的ESD事件的其它技术。

2. 发明申请

WO2011091064A1 HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs 审中-公开
标题翻译：用于RF IC的高电压，高频ESD保护电路
公开(公告)号：WO2011091064A1
公开(公告)日：2011-07-28
申请号：PCT/US2011/021752
申请日：2011-01-19
申请人： QUALCOMM Incorporated , WORLEY, Eugene, R. , MIN, ByungWook , WU, Der-woei
发明人： WORLEY, Eugene, R. , MIN, ByungWook , WU, Der-woei
IPC分类号： H03F1/52 , H01L27/02
CPC分类号： H03F1/52 , H01L27/0274
摘要： Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.
摘要翻译：描述了需要高压和高频操作的RFIC的改进的ESD保护电路。与预充电电路和二极管网络相结合的共源共栅接地栅极复位NFET（GGNFET）导致具有低电容和高导通电压的正ESD保护钳位。正电压ESD保护钳在正电压ESD脉冲期间为IC提供ESD保护。公开了一种负ESD保护钳的示例性实施例，其中使用偏置电路或电荷泵代替预充电电路，以允许偏置电路或电荷泵与二极管网络和共源共栅接地的组合门复位NFET，以提供防止负ESD电压脉冲的保护。在正或负电压ESD脉冲期间，正和负ESD保护钳的组合可为IC提供ESD保护。替代实施例通过仅使用正的ESD钳位来在正的ESD脉冲期间提供ESD保护来进一步减小ESD保护电路的电容，同时通过由RF前端的路径形成的放电路径来提供负的ESD脉冲的保护开关耦合到负ESD二极管。

3. 发明申请

WO2010105178A3 GATED DIODE HAVING AT LEAST ONE LIGHTLY-DOPED DRAIN (LDD) IMPLANT BLOCKED AND CIRCUITS AND METHODS EMPLOYING SAME 审中-公开
公开(公告)号：WO2010105178A3
公开(公告)日：2010-09-16
申请号：PCT/US2010/027172
申请日：2010-03-12
申请人： QUALCOMM INCORPORATED , WORLEY, Eugene, R.
发明人： WORLEY, Eugene, R.
IPC分类号： H01L29/861 , H01L23/60
摘要： Gated diodes, manufacturing methods, and related circuits are provided wherein at least one lightly-doped drain (LDD) implant is blocked in the gated diode to reduce its capacitance. In this manner, the gated diode may be used in circuits and other applications whose performance is sensitive to load capacitance while still obtaining the performance characteristics of a gated diode. These characteristics include fast turn-on times and high conductance, making the gated diodes disclosed herein well-suited for electro-static discharge (ESD) protection circuits as one application example. The examples of the gated diode disclosed herein include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region, wherein a P-N junction is formed. At least one LDD implant is blocked in the gated diode to reduce capacitance.

4. 发明申请

WO2010115137A1 LATERAL DIODE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：横向二极管及其制造方法
公开(公告)号：WO2010115137A1
公开(公告)日：2010-10-07
申请号：PCT/US2010/029830
申请日：2010-04-02
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , WORLEY, Eugene, R. , SIANSURI, Evan , DUNDIGAL, Sreeker, R.
发明人： JALILIZEINALI, Reza , WORLEY, Eugene, R. , SIANSURI, Evan , DUNDIGAL, Sreeker, R.
IPC分类号： H01L21/329 , H01L29/861 , H01L29/06
CPC分类号： H01L29/8611 , H01L29/0692 , H01L29/66128
摘要： An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed.
摘要翻译：可以在没有栅极并且在二极管的掺杂区域之间没有浅沟槽隔离区域的情况下制造具有快导通时间，低电容和低导通电阻的有源二极管。有源二极管中的短导通路径允许快速导通时间，并且缺少栅极氧化物降低有源二极管对极端电压的敏感性。有源二极管可以在集成电路中实现，以防止和减少静电放电（ESD）事件的损坏。有源二极管的制造是通过在盐析之前在二极管的掺杂区域之间沉积自对准硅化物块来实现的。在掺杂区域上形成自对准硅化物层之后，去除硅化物块。

5. 发明申请

WO2010104877A1 A CIRCUIT FOR MEASURING MAGNITUDE OF ELECTROSTATIC DISCHARGE (ESD) EVENTS FOR SEMICONDUCTOR CHIP BONDING 审中-公开
标题翻译：用于测量半导体芯片接合的静电放电（ESD）事件的电路的电路
公开(公告)号：WO2010104877A1
公开(公告)日：2010-09-16
申请号：PCT/US2010/026697
申请日：2010-03-09
申请人： QUALCOMM INCORPORATED , WORLEY, Eugene, R. , HENDERSON, Brian, Matthew
发明人： WORLEY, Eugene, R. , HENDERSON, Brian, Matthew
IPC分类号： G01R29/22 , G01R31/00
CPC分类号： G01R31/002 , H01L22/34 , H01L2224/16225
摘要： A circuit for recording a magnitude of an ESD event during semiconductor assembly includes a voltage divider connected between an input and a ground. The circuit also includes a measurement block having a recorder device. Each measurement block receives current from a segment of the voltage divider. The magnitude of the ESD event is determined based upon a read-out of the measurement devices after the ESD event. The recorder device may be a capacitor that would be damaged during the ESD event. During the ESD event the capacitor may be damaged. Reading out the recorder device determines if the magnitude of the ESD event exceeded a threshold magnitude that damages the capacitor.
摘要翻译：用于在半导体组件期间记录ESD事件的大小的电路包括连接在输入和地之间的分压器。电路还包括具有记录器装置的测量块。每个测量块从分压器的一个段接收电流。基于在ESD事件之后读出测量装置来确定ESD事件的大小。记录器设备可以是在ESD事件期间被损坏的电容器。在ESD事件期间，电容可能会损坏。读出记录器装置确定ESD事件的大小是否超过损坏电容器的阈值大小。

6. 发明申请

WO2005070108A2 ESD PROTECTION FOR INTEGRATED CIRCUITS HAVING ULTRA THIN GATE OXIDES 审中-公开
标题翻译：具有超薄栅极氧化物的集成电路的ESD保护
公开(公告)号：WO2005070108A2
公开(公告)日：2005-08-04
申请号：PCT/US2005/000615
申请日：2005-01-07
申请人： CONEXANT SYSTEMS, INC. , WORLEY, Eugene, R.
发明人： WORLEY, Eugene, R.
IPC分类号： H01L27/02 , H02H9/00 , H02H9/04
CPC分类号： H01L27/0251 , H01L27/0292
摘要： According to an exemplary embodiment, an integrated circuit includes a first circuit block having a first power bus. The integrated circuit further includes a second circuit block having a second power bus, where the first power bus is isolated from the second power bus. The integrated circuit further includes a first dedicated ESD bus, where the first dedicated ESD bus provides a discharge path from the first power bus to the second power bus and from the second power bus to the first power bus. The first power bus can be coupled to the first dedicated ESD bus by a first pair to bi-directional diodes, and the second power bus can be coupled to the first dedicated ESD bus by a second pair of bi-directional diodes.
摘要翻译：根据示例性实施例，集成电路包括具有第一电力总线的第一电路块。集成电路还包括具有第二电力总线的第二电路块，其中第一电力总线与第二电力总线隔离。集成电路还包括第一专用ESD总线，其中第一专用ESD总线提供从第一电力总线到第二电力总线以及从第二电力总线到第一电力总线的放电路径。第一电源总线可以通过第一对双向二极管耦合到第一专用ESD总线，并且第二电源总线可以通过第二对双向二极管耦合到第一专用ESD总线。

7. 发明申请

WO2002025735A3 DIODE WITH VARIABLE WIDTH METAL STRIPES FOR IMPROVED PROTECTION AGAINST ELECTROSTATIC DISCHARGE (ESD) CURRENT FAILURE 审中-公开
公开(公告)号：WO2002025735A3
公开(公告)日：2002-03-28
申请号：PCT/US2001/042241
申请日：2001-09-20
申请人： CONEXANT SYSTEMS, INC. , WORLEY, Eugene, R. , MATLOUBIAN, Mishel
发明人： WORLEY, Eugene, R. , MATLOUBIAN, Mishel
IPC分类号： H01L27/02
摘要： A diode for improved electrostatic discharge (ESD) protection against current failure includes a plurality of elongate anode and cathode conductor stripes each having first and second end portions of different widths to reduce current densities at feeder bus tie points, thereby reducing the possibility of current failure.

8. 发明公开

EP2406644A1 A CIRCUIT FOR MEASURING MAGNITUDE OF ELECTROSTATIC DISCHARGE (ESD) EVENTS FOR SEMICONDUCTOR CHIP BONDING 审中-公开
标题翻译：电路，其半导体芯片接合测量活动的量静电放电（ESD）
公开(公告)号：EP2406644A1
公开(公告)日：2012-01-18
申请号：EP10712197.2
申请日：2010-03-09
申请人： QUALCOMM Incorporated
发明人： WORLEY, Eugene, R. , HENDERSON, Brian, Matthew
IPC分类号： G01R29/22 , G01R31/00
CPC分类号： G01R31/002 , H01L22/34 , H01L2224/16225
摘要： A circuit for recording a magnitude of an ESD event during semiconductor assembly includes a voltage divider connected between an input and a ground. The circuit also includes a measurement block having a recorder device. Each measurement block receives current from a segment of the voltage divider. The magnitude of the ESD event is determined based upon a read-out of the measurement devices after the ESD event. The recorder device may be a capacitor that would be damaged during the ESD event. During the ESD event the capacitor may be damaged. Reading out the recorder device determines if the magnitude of the ESD event exceeded a threshold magnitude that damages the capacitor.

9. 发明授权

EP2526618B1 HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs 有权
公开(公告)号：EP2526618B1
公开(公告)日：2018-08-15
申请号：EP11702544.5
申请日：2011-01-19
申请人： Qualcomm Incorporated
发明人： WORLEY, Eugene, R. , MIN, ByungWook , WU, Der-woei
IPC分类号： H03F1/52 , H01L27/02
CPC分类号： H03F1/52 , H01L27/0274
摘要： Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.

10. 发明公开

EP2526618A1 HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs 审中-公开
标题翻译：高频高压ESD保护电路，集成电路高频
公开(公告)号：EP2526618A1
公开(公告)日：2012-11-28
申请号：EP11702544.5
申请日：2011-01-19
申请人： Qualcomm Incorporated
发明人： WORLEY, Eugene, R. , MIN, ByungWook , WU, Der-woei
IPC分类号： H03F1/52 , H01L27/02
CPC分类号： H03F1/52 , H01L27/0274
摘要： Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.

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