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1. 发明申请

WO2012125767A1 CHARGE PUMP ELECTROSTATIC DISCHARGE PROTECTION 审中-公开
标题翻译：充电泵静电放电保护
公开(公告)号：WO2012125767A1
公开(公告)日：2012-09-20
申请号：PCT/US2012/029129
申请日：2012-03-14
申请人： QUALCOMM INCORPORATED , SRIVASTAVA, Ankit , WORLEY, Eugene, R. , MIAO, Guoqing , QUAN, Xiaohong
发明人： SRIVASTAVA, Ankit , WORLEY, Eugene, R. , MIAO, Guoqing , QUAN, Xiaohong
IPC分类号： H03F1/52 , H01L27/02 , H02M3/07
CPC分类号： H03F1/52 , H01L27/0285 , H02M1/32 , H02M3/07
摘要： Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.
摘要翻译：用于放大器和使用电荷泵的其他电路的静电放电（ESD）保护技术。在示例性实施例中，响应于在电源电压节点和负输出电压节点之间检测到ESD事件，将第二飞跨电容器节点耦合到负输出电压节点的Vneg开关闭合。响应于在接地节点和负输出电压节点之间检测到ESD事件，将接地节点耦合到第二飞跨电容器节点的接地开关闭合。响应于在接地节点和负输出电压节点之间检测到ESD事件，Vneg开关进一步闭合。公开了用于在耦合到电荷泵的功率放大器的输出处提供片上快速恢复钳位以防止由标准IEC 61000-4-2定义的ESD事件的其它技术。

2. 发明申请

WO2012125766A3 CHARGE PUMP SURGE CURRENT REDUCTION 审中-公开
公开(公告)号：WO2012125766A3
公开(公告)日：2012-09-20
申请号：PCT/US2012/029128
申请日：2012-03-14
申请人： QUALCOMM INCORPORATED , QUAN, Xiaohong , SRIVASTAVA, Ankit , MIAO, Guoqing
发明人： QUAN, Xiaohong , SRIVASTAVA, Ankit , MIAO, Guoqing
IPC分类号： H02M3/07
摘要： Techniques for reducing surge current in charge pumps. In an exemplary embodiment, one or more switches coupling a terminal of a flying capacitor to a voltage supply are configured to have variable on-resistance. When the charge pump is configured to switch a gain mode from a lower gain to a higher gain, the one or more variable resistance switches are configured to have a decreasing resistance profile over time. In this manner, surge current drawn from the voltage supply at the outset of the gain switch may be limited, while the on-resistance during steady-state charging and discharging may be kept low. Similar techniques are provided to decrease the surge current from a bypass switch coupling the supply voltage to a positive output voltage of the charge pump.

3. 发明申请

WO2012103475A2 HIGH VOLTAGE TOLERANT DIFFERENTIAL RECEIVER 审中-公开
标题翻译：高压容差接收器
公开(公告)号：WO2012103475A2
公开(公告)日：2012-08-02
申请号：PCT/US2012/022965
申请日：2012-01-27
申请人： QUALCOMM Incorporated , SRIVASTAVA, Ankit , HUANG, Xuhao , QUAN, Xiaohong
发明人： SRIVASTAVA, Ankit , HUANG, Xuhao , QUAN, Xiaohong
IPC分类号： H03K19/0185
CPC分类号： G06F13/4072 , H03K19/018528
摘要： A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.
摘要翻译：高耐压差分接收器电路包括分压器梯形电路，该分压器梯形电路用于将差分输入信号分为大于分压器梯形电路的阈值电压的一半。传输门电路可操作以接收低于分压器阶梯的阈值电压的差分输入信号。分压器阶梯和传输门电路的输出提供给独立的比较器。来自比较器的输出相结合，在接收器电路的电压域产生一个信号。

4. 发明申请

WO2012103477A1 HIGH VOLTAGE TOLERANT RECEIVER 审中-公开
标题翻译：高耐压接收器
公开(公告)号：WO2012103477A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/022968
申请日：2012-01-27
申请人： QUALCOMM Incorporated , SRIVASTAVA, Ankit , HUANG, Xuhao , QUAN, Xiaohong
发明人： SRIVASTAVA, Ankit , HUANG, Xuhao , QUAN, Xiaohong
IPC分类号： H03K3/3565 , H03K19/0185
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.
摘要翻译：高耐压单端接收器电路包括分压器，其可操作地将大于分压器的阈值电压的半个单端输入信号分频。通路门电路用于接收低于分压器的阈值电压的单端信号。来自分压器的输出耦合到修改的施密特触发电路的第一输入端，以控制施密特触发电路的高阈值电平。来自通路电路的输出耦合到修改的施密特触发电路的第二输入，以控制施密特触发电路的低阈值电平。

5. 发明申请

WO2012009586A2 SQUELCH DETECTION CIRCUIT AND METHOD 审中-公开
标题翻译：检测电路和方法
公开(公告)号：WO2012009586A2
公开(公告)日：2012-01-19
申请号：PCT/US2011/044091
申请日：2011-07-15
申请人： QUALCOMM INCORPORATED , SRIVASTAVA, Ankit , QUAN, Xiaohong
发明人： SRIVASTAVA, Ankit , QUAN, Xiaohong
IPC分类号： H03G3/34 , H03K5/24
CPC分类号： H04B1/1027 , H03G3/341 , H03K5/2481
摘要： A squelch detection circuit and method involves a first comparator coupled to a complimentary input signal pair and having a first polarity output. A second comparator coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold.
摘要翻译：静噪检测电路和方法包括耦合到互补输入信号对并具有第一极性输出的第一比较器。耦合到互补输入信号对的第二比较器具有第二极性输出。与补偿输入信号对相关的偏移量建立正静噪阈值和负静噪阈值。耦合到第一比较器和第二比较器的校准单元产生包括阈值设置和校准设置的数字输出到第一比较器和第二比较器。数字输出可以与建立偏移量相关联，并校准正静噪阈值和负静噪阈值。

6. 发明申请

WO2011136964A1 LEVEL SHIFTER FOR DIFFERENTIAL SIGNALS WITH BALANCED TRANSITION TIMES 审中-公开
标题翻译：用于具有平衡过渡时间的差异信号的水平移位
公开(公告)号：WO2011136964A1
公开(公告)日：2011-11-03
申请号：PCT/US2011/032898
申请日：2011-04-18
申请人： QUALCOMM INCORPORATED , SRIVASTAVA, Ankit , QUAN, Xiaohong
发明人： SRIVASTAVA, Ankit , QUAN, Xiaohong
IPC分类号： H03K3/356 , H03K19/003 , H03K5/151 , H03K5/00
CPC分类号： H03K3/356113 , H03K5/151 , H03K19/00323 , H03K2005/00136
摘要： A level shifter (400) and method are provided for balancing rise and fall times of a signal. An input circuit (420, 413) receives a differential logic signal (Inp, Inn) with two complimentary logic levels. A level transition balancing circuit (420) balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element (430) stores and provides outputs (outp, ounn) of the level shifted versions of the logic levels. The level transition balancing circuit (420) includes a capacitor (421) in parallel with a field-effect transistor (422) for each input. The capacitor destabilizes inputs to the logic element and balances the transition using the capacitance and a level (435, 436) previously stored in the logic element.
摘要翻译：提供电平移位器（400）和方法来平衡信号的上升和下降时间。输入电路（420,413）接收具有两个互补逻辑电平的差分逻辑信号（Inp，Inn）。电平转换平衡电路（420）在逻辑电平的第一至第二过渡期间平衡每个互补逻辑电平的电平移位版本的上升和下降时间以及电平偏移。逻辑元件（430）存储并提供逻辑电平的电平转换版本的输出（outp，ounn）。电平转换平衡电路（420）包括与用于每个输入的场效应晶体管（422）并联的电容器（421）。电容器使逻辑元件的输入不稳定，并使用电容和先前存储在逻辑元件中的电平（435,436）平衡转换。

7. 发明申请

WO2012115880A1 DELAY CELL FOR CLOCK SIGNALS 审中-公开
标题翻译：延迟电池用于时钟信号
公开(公告)号：WO2012115880A1
公开(公告)日：2012-08-30
申请号：PCT/US2012/025695
申请日：2012-02-17
申请人： QUALCOM INCORPORATED , QUAN, Xiaohong , SRIVASTAVA, Ankit
发明人： QUAN, Xiaohong , SRIVASTAVA, Ankit
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03L7/16
摘要： An integrated circuit for delaying a clock signal using a delay cell is described. The integrated circuit includes a current starved inverter. The current starved inverter includes a switched capacitor current source with a first dummy inverter, a first amplifier coupled to the first dummy inverter and a first capacitor coupled to the first amplifier via a first switch. The current starved inverter also includes a first transistor coupled to the current source. The integrated circuit also includes a second capacitor. A delay applied to the clock signal is dependent on a ratio between the first capacitor and the second capacitor. The first capacitor and the second capacitor may be located in proximity such that process, voltage and temperature variations affect the first capacitor and the second capacitor similarly and the delay applied to the clock signal is independent of process, voltage and temperature variations
摘要翻译：描述了使用延迟单元来延迟时钟信号的集成电路。集成电路包括电流欠压逆变器。目前的饥饿逆变器包括具有第一虚拟反相器的开关电容器电流源，耦合到第一虚拟反相器的第一放大器和经由第一开关耦合到第一放大器的第一电容器。目前的饥饿逆变器还包括耦合到电流源的第一晶体管。集成电路还包括第二电容器。施加到时钟信号的延迟取决于第一电容器和第二电容器之间的比率。第一电容器和第二电容器可以位于接近处，使得过程，电压和温度变化类似地影响第一电容器和第二电容器，并且施加到时钟信号的延迟与过程，电压和温度变化无关

8. 发明申请

WO2011034861A1 DELAY-LOCKED LOOP HAVING A DELAY INDEPENDENT OF INPUT SIGNAL DUTY CYCLE VARIATION 审中-公开
标题翻译：具有延迟的延迟环路输入信号周期变化独立
公开(公告)号：WO2011034861A1
公开(公告)日：2011-03-24
申请号：PCT/US2010/048819
申请日：2010-09-14
申请人： QUALCOMM INCORPORATED , HUANG, Xuhao , QUAN, Xiaohong
发明人： HUANG, Xuhao , QUAN, Xiaohong
IPC分类号： H03L7/081 , H03K5/13
CPC分类号： H03L7/0812 , H03K5/13 , H03K5/133 , H03K5/1565 , H03K2005/00136
摘要： A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a "delay time", thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.
摘要翻译：延迟锁定环（DLL）使用延迟线将第一信号延迟“延迟时间”，从而产生第二信号。电容器以从第一信号的第一边缘开始的第一速率充电并持续到第二信号的边沿。然后电容器以第二速率放电，直到第一信号的另一个边沿。控制回路控制延迟时间，使得电容器的充电量与电容器放电量相同。延迟时间是恒定的并且基本上与第一信号的占空比的变化无关。在一个示例中，通过相对于第一信号占空比的变化按比例改变第一速率来实现占空比失真消除。在另一示例中，第一和第二速率与第一信号的占空比无关。

9. 发明申请

WO2010014993A1 ADAPTIVE BIAS CURRENT GENERATION FOR SWITCHED-CAPACITOR CIRCUITS 审中-公开
标题翻译：用于开关电容电路的自适应偏置电流产生
公开(公告)号：WO2010014993A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/052593
申请日：2009-08-03
申请人： QUALCOMM INCORPORATED , WANG, Chuanyang , QUAN, Xiaohong , BAZARJANI, Seyfollah
发明人： WANG, Chuanyang , QUAN, Xiaohong , BAZARJANI, Seyfollah
IPC分类号： H03F1/30 , H03F3/00 , H03F3/195 , H03F3/45
CPC分类号： H03F1/303 , H03F3/005 , H03F3/195 , H03F3/45188 , H03F2200/357 , H03F2200/447 , H03F2200/451 , H03M3/354 , H03M3/392 , H03M3/43 , H03M3/454
摘要： Techniques for adaptively generating bias current for a switched-capacitor circuit are described. The switched-capacitor circuit charges and discharges at least one switching capacitor at a sampling rate and may be a ADC that digitizes an analog signal at the sampling rate and provides digital samples. The switched-capacitor circuit may support multiple modes associated with different sampling rates. A bias circuit generates a bias current for the switched-capacitor circuit to be proportional to the sampling rate for a selected mode, to provide a bandwidth proportional to the sampling rate for an operational transconductance amplifier (OTA) within the switched-capacitor circuit, and to track changes in the switching capacitor(s) due to variations in integrated circuit (IC) process and temperature. The settling time of the switched-capacitor circuit may track with the multiple modes and across IC process and temperature variations.
摘要翻译：描述用于自适应地产生开关电容器电路的偏置电流的技术。开关电容电路以采样率对至少一个开关电容器进行充电和放电，并且可以是以采样率数字化模拟信号并提供数字采样的ADC。开关电容器电路可以支持与不同采样率相关联的多个模式。偏置电路产生用于开关电容器电路的偏置电流与所选模式的采样率成比例，以提供与开关电容器电路内的工作跨导放大器（OTA）的采样率成比例的带宽，以及以跟踪由于集成电路（IC）工艺和温度的变化而导致的开关电容器的变化。开关电容器电路的稳定时间可以跟踪多种模式，并跨过IC工艺和温度变化。

10. 发明申请

WO2009046151A1 DUAL-PATH CURRENT AMPLIFIER 审中-公开
标题翻译：双路电流放大器
公开(公告)号：WO2009046151A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/078510
申请日：2008-10-01
申请人： QUALCOMM Incorporated , QUAN, Xiaohong , PEDRALI-NOY, Marzio
发明人： QUAN, Xiaohong , PEDRALI-NOY, Marzio
IPC分类号： G05F3/26
CPC分类号： H03L7/099 , H03L7/107
摘要： A dual-path current amplifier having a slow high-gain path and a fast low-gain path is described. In one design, the slow high-gain path is implemented with a positive feedback loop and has a gain of greater than one and a bandwidth determined by a pole. The fast low-gain path has unity gain and wide bandwidth. The two signal paths receive an input current and provide first and seconds currents. A summer sums the first and second currents and provides an output current for the dual-path current amplifier. The dual-path current amplifier may be implemented with first and second current mirrors. The first current mirror may implement the fast low-gain path. The first and second current mirrors may be coupled together and implement the slow high-gain path. The first current mirror may be implemented with P-FETs. The second current mirror may be implemented with N-FETs, an operational amplifier, and a capacitor.
摘要翻译：描述了具有慢高增益路径和快速低增益路径的双路电流放大器。在一种设计中，慢的高增益路径是用正反馈回路实现的，并且具有大于1的增益和由极确定的带宽。快速低增益路径具有单位增益和宽带宽。两个信号路径接收输入电流并提供第一和第二电流。夏季对第一和第二电流求和，并为双路电流放大器提供输出电流。双路电流放大器可以用第一和第二电流镜来实现。第一电流镜可以实现快速低增益路径。第一和第二电流镜可以耦合在一起并实现慢速高增益路径。第一电流镜可以用P-FET实现。第二电流镜可以用N-FET，运算放大器和电容器来实现。

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