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1. 发明申请

WO2011146747A1 DC OFFSET CALIBRATION 审中-公开
标题翻译：直流偏移校准
公开(公告)号：WO2011146747A1
公开(公告)日：2011-11-24
申请号：PCT/US2011/037205
申请日：2011-05-19
申请人： QUALCOMM INCORPORATED , MIN, ByungWook , PARK, Chan Hong
发明人： MIN, ByungWook , PARK, Chan Hong
IPC分类号： H04B1/30
CPC分类号： H04B1/30
摘要： A mobile communication device comprises a plurality of receivers, a phase detection circuit, and a DC offset calibration circuit. Each receiver comprises a receiver chain and a divide-by-2 circuit that supplies Local Oscillating (LO) signal for the receiver chain. The LO signals leak to each receiver chain and create an undesirable DC offset voltage. The DC offset depends on an LNA gain and a phase relation among the LO leakages. In a first novel aspect, a two-dimensional DC offset calibration (DCOC) table is prepared for each receiver chain. In a second novel aspect, the phase detection circuit detects the phase relation among the LO leakages for each receiver chain. Based on the LNA gain and the detected phase relation of each receiver chain, a DCOC code is selected from a corresponding DCOC table such that the calibration circuit calibrates the DC offset for each receiver effectively and efficiently.
摘要翻译：移动通信设备包括多个接收机，相位检测电路和DC偏移校准电路。每个接收机包括一个接收器链和一个分频电路，为接收器链提供局部振荡（LO）信号。 LO信号泄漏到每个接收器链，并产生不期望的DC偏移电压。 DC偏移取决于LNA增益和LO泄漏之间的相位关系。在第一个新颖的方面，为每个接收机链准备二维DC偏移校准（DCOC）表。在第二个新颖的方面，相位检测电路检测每个接收器链的LO泄漏之间的相位关系。基于LNA增益和每个接收机链的检测相位关系，从相应的DCOC表中选择DCOC码，使得校准电路有效地高效地校准每个接收机的DC偏移。

2. 发明申请

WO2012058471A2 PACKAGE INDUCTANCE COMPENSATING TUNABLE CAPACITOR CIRCUIT 审中-公开
标题翻译：封装电感补偿电容电路
公开(公告)号：WO2012058471A2
公开(公告)日：2012-05-03
申请号：PCT/US2011/058152
申请日：2011-10-27
申请人： QUALCOMM Incorporated , MIN, ByungWook , WU, Der-Woei
发明人： MIN, ByungWook , WU, Der-Woei
IPC分类号： H03J3/20
CPC分类号： H03J3/20 , H01L23/66 , H01L2924/0002 , H03J2200/10 , H01L2924/00
摘要： An integrated circuit (IC) for compensating for a package inductance is disclosed. A first ground pad is directly connected to an on-chip ground node. A second IC ground pad is connected to the on-chip ground node via a tunable capacitor circuit, where the capacitance of the tunable capacitor circuit resonates with the package inductance at the operating frequency of the IC.
摘要翻译：公开了一种用于补偿封装电感的集成电路（IC）。第一接地焊盘直接连接到片上接地节点。第二IC接地焊盘通过可调电容电路连接到片上接地节点，其中可调谐电容器电路的电容在IC的工作频率处与封装电感谐振。

3. 发明申请

WO2011091064A1 HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs 审中-公开
标题翻译：用于RF IC的高电压，高频ESD保护电路
公开(公告)号：WO2011091064A1
公开(公告)日：2011-07-28
申请号：PCT/US2011/021752
申请日：2011-01-19
申请人： QUALCOMM Incorporated , WORLEY, Eugene, R. , MIN, ByungWook , WU, Der-woei
发明人： WORLEY, Eugene, R. , MIN, ByungWook , WU, Der-woei
IPC分类号： H03F1/52 , H01L27/02
CPC分类号： H03F1/52 , H01L27/0274
摘要： Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.
摘要翻译：描述了需要高压和高频操作的RFIC的改进的ESD保护电路。与预充电电路和二极管网络相结合的共源共栅接地栅极复位NFET（GGNFET）导致具有低电容和高导通电压的正ESD保护钳位。正电压ESD保护钳在正电压ESD脉冲期间为IC提供ESD保护。公开了一种负ESD保护钳的示例性实施例，其中使用偏置电路或电荷泵代替预充电电路，以允许偏置电路或电荷泵与二极管网络和共源共栅接地的组合门复位NFET，以提供防止负ESD电压脉冲的保护。在正或负电压ESD脉冲期间，正和负ESD保护钳的组合可为IC提供ESD保护。替代实施例通过仅使用正的ESD钳位来在正的ESD脉冲期间提供ESD保护来进一步减小ESD保护电路的电容，同时通过由RF前端的路径形成的放电路径来提供负的ESD脉冲的保护开关耦合到负ESD二极管。

4. 发明授权

EP2526618B1 HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs 有权
公开(公告)号：EP2526618B1
公开(公告)日：2018-08-15
申请号：EP11702544.5
申请日：2011-01-19
申请人： Qualcomm Incorporated
发明人： WORLEY, Eugene, R. , MIN, ByungWook , WU, Der-woei
IPC分类号： H03F1/52 , H01L27/02
CPC分类号： H03F1/52 , H01L27/0274
摘要： Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.

5. 发明公开

EP2633553A2 PACKAGE INDUCTANCE COMPENSATING TUNABLE CAPACITOR CIRCUIT 审中-公开
标题翻译： EINSTELLBARE KONDENSATORSCHALTUNG MITGEHÄUSEINDUKTANZKOMPENSATION
公开(公告)号：EP2633553A2
公开(公告)日：2013-09-04
申请号：EP11782704.8
申请日：2011-10-27
申请人： Qualcomm Incorporated
发明人： MIN, ByungWook , WU, Der-Woei
IPC分类号： H01L23/66 , H03J1/00
CPC分类号： H03J3/20 , H01L23/66 , H01L2924/0002 , H03J2200/10 , H01L2924/00
摘要： An integrated circuit (IC) for compensating for a package inductance is disclosed. A first ground pad is directly connected to an on-chip ground node. A second IC ground pad is connected to the on-chip ground node via a tunable capacitor circuit, where the capacitance of the tunable capacitor circuit resonates with the package inductance at the operating frequency of the IC.
摘要翻译：公开了一种用于补偿封装电感的集成电路（IC）。第一接地焊盘直接连接到片上接地节点。第二IC接地焊盘通过可调电容电路连接到片上接地节点，其中可调谐电容器电路的电容在IC的工作频率处与封装电感谐振。

6. 发明公开

EP2526618A1 HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs 审中-公开
标题翻译：高频高压ESD保护电路，集成电路高频
公开(公告)号：EP2526618A1
公开(公告)日：2012-11-28
申请号：EP11702544.5
申请日：2011-01-19
申请人： Qualcomm Incorporated
发明人： WORLEY, Eugene, R. , MIN, ByungWook , WU, Der-woei
IPC分类号： H03F1/52 , H01L27/02
CPC分类号： H03F1/52 , H01L27/0274
摘要： Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.

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