专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2005107428A2 DYNAMIC VOLTAGE SCALING SYSTEM 审中-公开
标题翻译：动态电压调节系统
公开(公告)号：WO2005107428A2
公开(公告)日：2005-11-17
申请号：PCT/US2005/016095
申请日：2005-05-05
申请人： QUALCOMM INCORPORATED , HENDERSON, Eric Lee , DROP, Michael , KAZI, Tauseef
发明人： HENDERSON, Eric Lee , DROP, Michael , KAZI, Tauseef
IPC分类号： G06F1/32 , H04L7/00
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： Methods and apparatus for implementing a Dynamic Voltage Scaling (DVS) system are presented herein. In one embodiment, an embedded delay checker (EDC) cell is used to measure the actual activity and delay of a critical path within a microprocessor core, which is the basis for dynamically altering the voltage to the core. In another embodiment, a slaved ring oscillator (SRO) cell is placed adjacent to the microprocessor core and is used along with EDC cells to provide redundancy to a DVS system.
摘要翻译：本文介绍了实现动态电压调节（DVS）系统的方法和设备。在一个实施例中，使用嵌入式延迟检查器（EDC）单元来测量微处理器内核内的关键路径的实际活动和延迟，这是动态地改变对核心的电压的基础。在另一个实施例中，从属环形振荡器（SRO）单元放置在与微处理器核心相邻的位置处，并与EDC单元一起使用以向DVS系统提供冗余。

2. 发明申请

WO2010054124A1 SYSTEMS AND METHODS FOR IMPROVING DIGITAL SYSTEM SIMULATION SPEED BY CLOCK PHASE GATING 审中-公开
标题翻译：通过时钟相位增益改进数字系统模拟速度的系统和方法
公开(公告)号：WO2010054124A1
公开(公告)日：2010-05-14
申请号：PCT/US2009/063454
申请日：2009-11-05
申请人： QUALCOMM Incorporated , KAZI, Tauseef , YU, Haobo , CAI, Lukai , SRIDHARAN, Mahesh , CHAIYAKUL, Viraphol , CHAN, Wah
发明人： KAZI, Tauseef , YU, Haobo , CAI, Lukai , SRIDHARAN, Mahesh , CHAIYAKUL, Viraphol , CHAN, Wah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.
摘要翻译：描述了一种用于模拟数字系统的装置。该装置包括处理器和与处理器电子通信的存储器。可由处理器执行的指令存储在存储器中。开始一个模拟工具。仿真工具能够模拟多个组件。对于至少一个组件，时钟相位被调整为关闭。模拟包括至少一个组件的数字系统。模拟不会模拟至少一个组件的时钟相位。

3. 发明申请

WO2005109021A1 SYSTEMS AND METHODS FOR TESTING PACKAGED DIES 审中-公开
标题翻译：用于测试包装袋的系统和方法
公开(公告)号：WO2005109021A1
公开(公告)日：2005-11-17
申请号：PCT/US2005/010780
申请日：2005-03-31
申请人： QUALCOMM INCORPORATED , KAZI, Tauseef , GEMAR, Jeff , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： KAZI, Tauseef , GEMAR, Jeff , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： G01R31/30
CPC分类号： G01R31/3008 , G01R31/318505 , G01R31/318533
摘要： A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.
摘要翻译：主模具和堆叠模具包括在相同的组件封装中。在主管芯上实现传输门（370），并且能够在主管芯和堆叠管芯之间的连接（318）中接收泄漏电流，并将泄漏电流传导到接合焊盘（344）可以在包装外部访问。因此，可以在封装模具之后测试主模具和堆叠模具之间的连接性。传输门在高速测试和正常运行期间被禁用。封装还可以包括多路复用器（364），其在高速测试期间被启用以在封装级别输入和输出测试信号。方向信号用于指示测试信号是否被输入到主模具或从主模块输出。

4. 发明申请

WO2010054123A1 METHODS AND APPARATUS FOR CLOCK SIMULATION WITH CALIBRATION 审中-公开
标题翻译：用于时钟模拟与校准的方法和装置
公开(公告)号：WO2010054123A1
公开(公告)日：2010-05-14
申请号：PCT/US2009/063452
申请日：2009-11-05
申请人： QUALCOMM Incorporated , CAI, Lukai , SRIDHARAN, Mahesh , KAZI, Tauseef
发明人： CAI, Lukai , SRIDHARAN, Mahesh , KAZI, Tauseef
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for clock modeling in a simulation tool is described. An internal time (I) may be defined that governs the simulator tool's clock period. An external time (E) may be defined. The internal time may have a smaller resolution than the external time. A calibration period (C) may be defined for the clock. The calibration period may be smaller than 0.5E and greater than I. The largest inaccuracy of any clock edge may be monitored, and the clock may be calibrated if the largest inaccuracy is greater than (C-1).
摘要翻译：描述了模拟工具中时钟建模的方法。可以定义控制模拟器工具的时钟周期的内部时间（I）。可以定义外部时间（E）。内部时间可能比外部时间更小的分辨率。可以为时钟定义校准周期（C）。校准周期可以小于0.5E且大于I.可以监视任何时钟沿的最大不准确度，并且如果最大不准确度大于（C-1），则可校准时钟。

5. 发明公开

EP3411775A2 FORCED IDLING OF MEMORY SUBSYSTEMS 审中-公开
公开(公告)号：EP3411775A2
公开(公告)日：2018-12-12
申请号：EP17701232.5
申请日：2017-01-06
申请人： Qualcomm Incorporated
发明人： ALAVOINE, Olivier , LEE, Sejoong , KAZI, Tauseef , BOOTH, Simon , REGINI, Edoardo , JAKUSHOKAS, Renatas , PATODIA, Saurabh , GEMAR, Jeffrey , LO, Haw-Jing , CHAMARTY, Vinod , ANDREEV, Boris , SHEN, Tao , BHASKARA, Aravind , WANG, Wenbiao , MOLLOY, Stephen
IPC分类号： G06F1/32
CPC分类号： G06F3/0659 , G06F1/3275 , G06F3/0625 , G06F3/0673 , G06F12/08 , Y02D10/13 , Y02D10/14
摘要： Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

6. 发明公开

EP3341813A1 POWER MULTIPLEXER FOR AN INTEGRATED CIRCUIT 有权
公开(公告)号：EP3341813A1
公开(公告)日：2018-07-04
申请号：EP16745962.7
申请日：2016-07-21
申请人： Qualcomm Incorporated
发明人： CAO, Lipeng , KAZI, Tauseef , ARTIERI, Alain Dominique
IPC分类号： G06F1/32
摘要： An integrated circuit is provided with a low-power island including embedded memory power domains that may selectively couple to either an active-mode power supply voltage supplied on a first power rail or to a sleep-mode power supply voltage supplied on a second power rail.

7. 发明申请

WO2017136099A3 FORCED IDLING OF MEMORY SUBSYSTEMS 审中-公开
公开(公告)号：WO2017136099A3
公开(公告)日：2017-08-10
申请号：PCT/US2017/012514
申请日：2017-01-06
申请人： QUALCOMM INCORPORATED
发明人： ALAVOINE, Olivier , LEE, Sejoong , KAZI, Tauseef , BOOTH, Simon , REGINI, Edoardo , JAKUSHOKAS, Renatas , PATODIA, Saurabh , GEMAR, Jeffrey , LO, Haw-Jing , CHAMARTY, Vinod , ANDREEV, Boris , SHEN, Tao , BHASKARA, Aravind , WANG, Wenbiao , MOLLOY, Stephen
IPC分类号： G06F1/32
摘要： Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

8. 发明申请

WO2017136099A2 FORCED IDLING OF MEMORY SUBSYSTEMS 审中-公开
标题翻译：记忆子系统的强制性IDLING
公开(公告)号：WO2017136099A2
公开(公告)日：2017-08-10
申请号：PCT/US2017/012514
申请日：2017-01-06
申请人： QUALCOMM INCORPORATED
发明人： ALAVOINE, Olivier , LEE, Sejoong , KAZI, Tauseef , BOOTH, Simon , REGINI, Edoardo , JAKUSHOKAS, Renatas , PATODIA, Saurabh , GEMAR, Jeffrey , LO, Haw-Jing , CHAMARTY, Vinod , ANDREEV, Boris , SHEN, Tao , BHASKARA, Aravind , WANG, Wenbiao , MOLLOY, Stephen
CPC分类号： G06F3/0659 , G06F1/3275 , G06F3/0625 , G06F3/0673 , G06F12/08 , Y02D10/13 , Y02D10/14
摘要： Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.
摘要翻译：各种方面包括用于管理计算设备上的存储器子系统的方法。各种方面方法可以包括确定强制计算设备上的存储器子系统进入低功率模式的时间段，在确定的时间段期间禁止对存储器子系统的存储器访问请求，迫使存储器子系统进入低功率模式所确定的时间周期，并且响应于所确定的时间段的期满，在所确定的时间段期间向存储器子系统执行存储器访问请求。

9. 发明申请

WO2003023581A2 UNIVERSAL PROGRAMMABLE DELAY CELL 审中-公开
标题翻译：通用可编程延迟电池
公开(公告)号：WO2003023581A2
公开(公告)日：2003-03-20
申请号：PCT/US2002/028676
申请日：2002-09-10
申请人： QUALCOMM INCORPORATED
发明人： KAZI, Tauseef
IPC分类号： G06F1/10
CPC分类号： G06F17/5045 , G06F1/10
摘要： A circuit and method for minimizing clock skew in an integrated circuit. The circuit is configured as a combination of delay elements and connection matrices that by connecting input and output pins in the connection matrix the circuit designer can select the required delay value. The connection matrices are defined in the circuit synthesis process as non routable areas therefore the programmable delay cells are programed after the circuit design is complete without requiring the circuit to be re routed. By inserting standard programmable delay cells in the clock tree the circuit designer can build in adjustable compensation for a wide range of clock skew.
摘要翻译：一种用于最小化集成电路中的时钟偏移的电路和方法。该电路被配置为延迟元件和连接矩阵的组合，通过连接矩阵中的输入和输出引脚，电路设计者可以选择所需的延迟值。连接矩阵在电路合成过程中被定义为不可路由的区域，因此可在电路设计完成之后对可编程延迟单元进行编程，而不需要重新路由电路。通过在时钟树中插入标准可编程延迟单元，电路设计人员可以在宽范围的时钟偏移范围内构建可调补偿。

10. 发明授权

EP3341813B1 POWER MULTIPLEXER FOR AN INTEGRATED CIRCUIT 有权
公开(公告)号：EP3341813B1
公开(公告)日：2020-03-25
申请号：EP16745962.7
申请日：2016-07-21
申请人： Qualcomm Incorporated
发明人： CAO, Lipeng , KAZI, Tauseef , ARTIERI, Alain Dominique
IPC分类号： G06F1/3203

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式