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1. 发明申请

WO2018071153A3 DUTY CYCLE CONTROL BUFFER CIRCUIT 审中-公开
公开(公告)号：WO2018071153A3
公开(公告)日：2018-04-19
申请号：PCT/US2017/052739
申请日：2017-09-21
申请人： QUALCOMM INCORPORATED
发明人： PAUL, Animesh , CHEN, Xinhua
IPC分类号： H03K5/156 , H03K5/00
摘要： Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit generally includes a first clock-generation stage comprising first cascode-connected transistors the first cascode-connected transistors having gates coupled to a first input clock node. The multi-stage clock generation circuit may also include a second clock-generation stage comprising second cascode-connected transistors, the second cascode-connected transistors having gates coupled to a second input clock node. A first transistor may be coupled to the second cascode-connected transistors, the first transistor having a gate coupled to drains of the first cascode-connected transistors.

2. 发明申请

WO2018071153A2 DUTY CYCLE CONTROL BUFFER CIRCUIT 审中-公开
公开(公告)号：WO2018071153A2
公开(公告)日：2018-04-19
申请号：PCT/US2017/052739
申请日：2017-09-21
申请人： QUALCOMM INCORPORATED
发明人： PAUL, Animesh , CHEN, Xinhua
IPC分类号： H03K5/156
CPC分类号： H03K5/1565 , H03K5/134 , H03K2005/00026 , H04B1/40
摘要： Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit generally includes a first clock-generation stage comprising first cascode-connected transistors the first cascode-connected transistors having gates coupled to a first input clock node. The multi-stage clock generation circuit may also include a second clock-generation stage comprising second cascode-connected transistors, the second cascode-connected transistors having gates coupled to a second input clock node. A first transistor may be coupled to the second cascode-connected transistors, the first transistor having a gate coupled to drains of the first cascode-connected transistors.
摘要翻译：本公开的某些方面一般涉及生成时钟信号。例如，本公开的某些方面提供了一种多级时钟生成电路。多级时钟生成电路通常包括第一时钟生成级，其包括第一共源共栅连接的晶体管，第一共源共栅连接的晶体管具有耦合到第一输入时钟节点的栅极。多级时钟产生电路还可以包括具有第二共源共栅连接的晶体管的第二时钟发生级，第二共源共栅连接的晶体管具有连接到第二输入时钟节点的栅极。第一晶体管可以耦合到第二共源共栅连接的晶体管，第一晶体管具有耦合到第一共源共栅连接的晶体管的漏极的栅极。

3. 发明申请

WO2018052982A2 RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT 审中-公开
标题翻译：基于重新计时的时钟生成和剩余边带（RSB）增强电路
公开(公告)号：WO2018052982A2
公开(公告)日：2018-03-22
申请号：PCT/US2017/051336
申请日：2017-09-13
申请人： QUALCOMM INCORPORATED
发明人： PAUL, Animesh , ZHUANG, Jingcheng , CHEN, Xinhua , SRIDHARA, Ravi
IPC分类号： H03K5/156
摘要： Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.
摘要翻译：本公开的某些方面一般涉及用于生成时钟信号的方法和装置。例如，本公开的某些方面提供了一种时钟生成电路。时钟生成电路可以包括与第二晶体管共源共栅连接的第一晶体管，其中电路的输入时钟节点耦合到第一和第二晶体管的栅极。时钟生成电路还可以包括分频器电路，该分频器电路具有耦合到输入时钟节点的输入，其中分频器电路的输出耦合到第二晶体管的源极，并且其中电路的输出节点耦合到第一和第二晶体管的漏极。

4. 发明申请

WO2018013406A1 FRACTIONAL-N PHASE LOCKED LOOP DELTA SIGMA MODULATOR NOISE REDUCTION USING CHARGE PUMP INTERPOLATION 审中-公开
标题翻译：使用电荷泵插值降低N相锁定环路DELTA SIGMA MODULATOR的噪声
公开(公告)号：WO2018013406A1
公开(公告)日：2018-01-18
申请号：PCT/US2017/040978
申请日：2017-07-06
申请人： QUALCOMM INCORPORATED
发明人： ZHUANG, Jingcheng , CHEN, Xinhua , BOSSU, Frederic , TANG, Yiwu
IPC分类号： H03L7/089 , H03L7/191 , H03L7/197
CPC分类号： H03L7/087 , H03L7/0898 , H03L7/099 , H03L7/191 , H03L7/1974 , H03L7/1976 , H04L7/033
摘要： A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.
摘要翻译：锁相环具有包括在反馈路径中的分频器。分频器产生第一个输出和一个延迟输出。锁相环还包括一个电荷泵，用于根据分频器的第一输出和延迟输出产生输出电流。

5. 发明申请

WO2014133783A1 PHASE-LOCKED LOOP USING DUAL LOOP MODE TO ACHIEVE FAST RESETTLING 审中-公开
标题翻译：使用双循环模式的相位锁定环来实现快速重置
公开(公告)号：WO2014133783A1
公开(公告)日：2014-09-04
申请号：PCT/US2014/016383
申请日：2014-02-14
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Xinhua , TANG, Yiwu
IPC分类号： H03L7/093 , H03L7/107
CPC分类号： H03L7/0891 , H03L7/093 , H03L7/107
摘要： A PLL operates in a first low bandwidth mode using a first control loop and in a second high bandwidth mode using a second control loop. The PLL includes a VCO that generates an output signal at a desired frequency used by a transmitter. When the transmitter switches from a High Power mode (HP TX) to a Low Power mode (LP TX), the PLL is perturbed (VCO no longer generates the desired frequency) and must resettle within an allocated time. In one example, the VCO frequency is 3.96 GHz and the settling time requirement is 25 microseconds. Upon switching from HP TX to LP TX, the PLL is switched to the second high bandwidth mode 15 microseconds and is then switched back to the first low bandwidth mode. The PLL resettles to within 1ppm of the initial VCO frequency of 3.96 GHz within the allocated 25 microseconds.
摘要翻译： PLL使用第一控制环路在第一低带宽模式下工作，并且在第二高带宽模式中使用第二控制环路工作。 PLL包括VCO，其产生以发射机使用的期望频率的输出信号。当发射机从高功率模式（HP TX）切换到低功耗模式（LP TX）时，PLL被扰乱（VCO不再产生所需频率），并且必须在分配的时间内重新定位。在一个示例中，VCO频率为3.96GHz，建立时间要求为25微秒。从HP TX切换到LP TX时，PLL将切换到第二个高带宽模式15微秒，然后切换回第一个低带宽模式。在分配的25微秒内，PLL将重置为3.96 GHz的初始VCO频率的1ppm以内。

6. 发明授权

EP3513494B1 RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT 有权
公开(公告)号：EP3513494B1
公开(公告)日：2020-04-08
申请号：EP17777700.0
申请日：2017-09-13
申请人： Qualcomm Incorporated
发明人： PAUL, Animesh , ZHUANG, Jingcheng , CHEN, Xinhua , SRIDHARA, Ravi
IPC分类号： H03K5/156 , H03K21/02

7. 发明申请

WO2018052982A3 RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT 审中-公开
标题翻译：基于重新计时的时钟生成和剩余边带（RSB）增强电路
公开(公告)号：WO2018052982A3
公开(公告)日：2018-03-22
申请号：PCT/US2017/051336
申请日：2017-09-13
申请人： QUALCOMM INCORPORATED
发明人： PAUL, Animesh , ZHUANG, Jingcheng , CHEN, Xinhua , SRIDHARA, Ravi
IPC分类号： H03K5/156 , H03K21/02
摘要： Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor (402) connected in cascode with a second transistor (404), wherein an input clock (Clk_in) node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit (406) having an input coupled to the input clock node, wherein an output (Div_out) of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node (Clk_out) of the circuit is coupled to drains of the first and second transistors.
摘要翻译：本公开的某些方面一般涉及用于生成时钟信号的方法和装置。例如，本公开的某些方面提供了一种时钟生成电路。时钟生成电路可以包括与第二晶体管（404）共源共栅连接的第一晶体管（402），其中电路的输入时钟（Clk_in）节点耦合到第一和第二晶体管的栅极。时钟生成电路还可以包括分频器电路（406），该分频器电路具有耦合到输入时钟节点的输入，其中分频器电路的输出（Div_out）被耦合到第二晶体管的源极，并且其中输出节点（Clk_out）耦合到第一和第二晶体管的漏极。

8. 发明公开

EP3513494A2 RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT 有权
公开(公告)号：EP3513494A2
公开(公告)日：2019-07-24
申请号：EP17777700.0
申请日：2017-09-13
申请人： Qualcomm Incorporated
发明人： PAUL, Animesh , ZHUANG, Jingcheng , CHEN, Xinhua , SRIDHARA, Ravi
IPC分类号： H03K5/156 , H03K21/02
摘要： Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.

9. 发明申请

WO2019060124A1 PLL POST DIVIDER PHASE CONTINUITY 审中-公开
公开(公告)号：WO2019060124A1
公开(公告)日：2019-03-28
申请号：PCT/US2018/048957
申请日：2018-08-30
申请人： QUALCOMM INCORPORATED
发明人： ZHUANG, Jingcheng , HU, Jianyun , PAUL, Animesh , CHEN, Xinhua , BOSSU, Frederic
IPC分类号： H03L7/08 , H03L7/197
CPC分类号： H03L7/1803 , H03C3/0975 , H03L7/0805 , H03L7/093 , H03L7/0992 , H03L7/1976 , H04L7/0008 , H04L7/033
摘要： A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

10. 发明申请

WO2018217339A1 DISTRIBUTED DIFFERENTIAL INTERCONNECT 审中-公开
公开(公告)号：WO2018217339A1
公开(公告)日：2018-11-29
申请号：PCT/US2018/028368
申请日：2018-04-19
申请人： QUALCOMM INCORPORATED
发明人： VALLABHANENI, Madhukar , KOPPASSERY, Girish , CHEN, Xinhua , ZHUANG, Jingcheng
IPC分类号： H04L25/02 , H01B11/00
CPC分类号： H04B3/28 , H01R9/034 , H01R9/11 , H01R11/05 , H01R12/00 , H01R12/7076 , H01R12/775 , H04L25/00 , H04L25/0274 , H04L25/085 , H05K1/0233
摘要： An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.

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