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1. 发明申请

WO2018052982A3 RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT 审中-公开
标题翻译：基于重新计时的时钟生成和剩余边带（RSB）增强电路
公开(公告)号：WO2018052982A3
公开(公告)日：2018-03-22
申请号：PCT/US2017/051336
申请日：2017-09-13
申请人： QUALCOMM INCORPORATED
发明人： PAUL, Animesh , ZHUANG, Jingcheng , CHEN, Xinhua , SRIDHARA, Ravi
IPC分类号： H03K5/156 , H03K21/02
摘要： Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor (402) connected in cascode with a second transistor (404), wherein an input clock (Clk_in) node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit (406) having an input coupled to the input clock node, wherein an output (Div_out) of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node (Clk_out) of the circuit is coupled to drains of the first and second transistors.
摘要翻译：本公开的某些方面一般涉及用于生成时钟信号的方法和装置。例如，本公开的某些方面提供了一种时钟生成电路。时钟生成电路可以包括与第二晶体管（404）共源共栅连接的第一晶体管（402），其中电路的输入时钟（Clk_in）节点耦合到第一和第二晶体管的栅极。时钟生成电路还可以包括分频器电路（406），该分频器电路具有耦合到输入时钟节点的输入，其中分频器电路的输出（Div_out）被耦合到第二晶体管的源极，并且其中输出节点（Clk_out）耦合到第一和第二晶体管的漏极。

2. 发明申请

WO2010132870A1 RECEIVER WITH BALANCED I/Q TRANSFORMER 审中-公开
标题翻译：接收器与平衡I / Q变压器
公开(公告)号：WO2010132870A1
公开(公告)日：2010-11-18
申请号：PCT/US2010/035079
申请日：2010-05-17
申请人： QUALCOMM Incorporated , CHANG, Li-Chung , BHAGAT, Maulin P. , LEE, Hanil , SRIDHARA, Ravi
发明人： CHANG, Li-Chung , BHAGAT, Maulin P. , LEE, Hanil , SRIDHARA, Ravi
IPC分类号： H03D7/14
CPC分类号： H03D7/1466 , H03D7/1458 , H03D7/165 , H03D2200/0082
摘要： A receiver with a balanced I/Q transformer is described. In an exemplary design, the receiver includes an LNA that amplifies a received RF signal and provides a single-ended RF signal to the balanced I/Q transformer. The balanced I/Q transformer includes at least one primary coil and first and second secondary coils. The first secondary coil is magnetically coupled to the at least one primary coil and provides a first differential RF signal to a first mixer. The second secondary coil is magnetically coupled to the at least one primary coil and provides a second differential RF signal to a second mixer. The first and second mixers downconvert the first and second differential RF signals with I and Q LO signals, respectively, and provide differential I and Q downconverted signals. The primary and secondary coils may be fabricated on two conductive layers of an integrated circuit.
摘要翻译：描述了具有平衡I / Q变压器的接收机。在示例性设计中，接收机包括放大接收到的RF信号并向平衡I / Q变换器提供单端RF信号的LNA。平衡I / Q变压器包括至少一个初级线圈和第一和第二次级线圈。第一次级线圈磁耦合到至少一个初级线圈，并向第一混频器提供第一差分RF信号。第二次级线圈磁耦合到至少一个初级线圈，并将第二差分RF信号提供给第二混频器。第一和第二混频器分别用I和Q LO信号下变频第一和第二差分RF信号，并提供差分I和Q下变频信号。初级和次级线圈可以制造在集成电路的两个导电层上。

3. 发明申请

WO2009076562A1 TRACKING FILTER FOR A RECEIVER 审中-公开
标题翻译：跟踪接收器的过滤器
公开(公告)号：WO2009076562A1
公开(公告)日：2009-06-18
申请号：PCT/US2008/086488
申请日：2008-12-11
申请人： QUALCOMM Incorporated , SAHOTA, Gurkanwal Kamal , NARATHONG, Chiewcharn , SRIDHARA, Ravi
发明人： SAHOTA, Gurkanwal Kamal , NARATHONG, Chiewcharn , SRIDHARA, Ravi
IPC分类号： H04B1/18 , H03L7/085
CPC分类号： H04B1/18
摘要： A tracking filter for attenuating out-of-band signals and adjacent channel signals in a receiver is described. In one exemplary design, an apparatus includes a tracking filter, an LNA, and a downconverter. The tracking filter includes a summer, a filter, and an upconverter. The summer subtracts a feedback signal from an input signal and provides a first signal. The LNA amplifies the first signal and provides a second signal. The downconverter frequency downconverts the second signal and provides an output signal. The filter filters (e.g., differentiates) the output signal and provides a third signal. The filter blocks a desired signal and passes out-of-band signal components. The upconverter frequency upconverts the third signal and provides a fourth signal from which the feedback signal is derived. The tracking filter has an equivalent bandpass filter response and a variable center frequency determined based on the frequency of the desired signal.
摘要翻译：描述了用于衰减接收机中的带外信号和相邻信道信号的跟踪滤波器。在一个示例性设计中，装置包括跟踪滤波器，LNA和下变频器。跟踪过滤器包括夏季，过滤器和上变频器。夏季从输入信号中减去反馈信号并提供第一信号。 LNA放大第一个信号并提供第二个信号。下变频器降频转换第二信号并提供输出信号。滤波器（例如，微分）输出信号并提供第三信号。滤波器阻挡所需的信号并传出带外信号分量。上变频器对第三信号进行上变频，并提供第四信号，从中得到反馈信号。跟踪滤波器具有等效的带通滤波器响应和基于期望信号的频率确定的可变中心频率。

4. 发明申请

WO2018052982A2 RE-TIMING BASED CLOCK GENERATION AND RESIDUAL SIDEBAND (RSB) ENHANCEMENT CIRCUIT 审中-公开
标题翻译：基于重新计时的时钟生成和剩余边带（RSB）增强电路
公开(公告)号：WO2018052982A2
公开(公告)日：2018-03-22
申请号：PCT/US2017/051336
申请日：2017-09-13
申请人： QUALCOMM INCORPORATED
发明人： PAUL, Animesh , ZHUANG, Jingcheng , CHEN, Xinhua , SRIDHARA, Ravi
IPC分类号： H03K5/156
摘要： Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.
摘要翻译：本公开的某些方面一般涉及用于生成时钟信号的方法和装置。例如，本公开的某些方面提供了一种时钟生成电路。时钟生成电路可以包括与第二晶体管共源共栅连接的第一晶体管，其中电路的输入时钟节点耦合到第一和第二晶体管的栅极。时钟生成电路还可以包括分频器电路，该分频器电路具有耦合到输入时钟节点的输入，其中分频器电路的输出耦合到第二晶体管的源极，并且其中电路的输出节点耦合到第一和第二晶体管的漏极。

5. 发明申请

WO2017204902A1 PHASE CONTINUITY TECHNIQUE FOR FREQUENCY SYNTHESIS 审中-公开
标题翻译：用于频率综合的相位连续技术
公开(公告)号：WO2017204902A1
公开(公告)日：2017-11-30
申请号：PCT/US2017/025547
申请日：2017-03-31
申请人： QUALCOMM INCORPORATED
发明人： ZANUSO, Marco , ELBADRY, Mohammad , HUNG, Tsai-Pi , SRIDHARA, Ravi , GATTA, Francesco , ZHUANG, Jingcheng
IPC分类号： H03L7/14
CPC分类号： H04L7/033 , H03L7/14 , H03L7/143 , H03L7/1976 , H03L2207/08 , H04L5/14 , H04L69/28 , H04W84/042
摘要： A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.
摘要翻译：相位锁定环（PLL）内的相位不连续性缓解实现提高了无线电接入技术的吞吐量。在断开PLL的一些器件（如本地振荡器（LO）分频器）时，通过保持PLL的相位来改善吞吐量。在一个实例中，当PLL断电时，PLL的一个或多个部分的Δ-Σ调制器以PLL的参考时钟为时钟。当第一个锁相环打开时，此实现可保持相位连续性。

6. 发明申请

WO2009036399A1 LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE 审中-公开
标题翻译：本地振荡器缓冲器和具有可调整尺寸的混频器
公开(公告)号：WO2009036399A1
公开(公告)日：2009-03-19
申请号：PCT/US2008/076324
申请日：2008-09-12
申请人： QUALCOMM Incorporated , ANIRUDDHAN, Sankaran , NARATHONG, Chiewcharn , SRIDHARA, Sriramgopal , SRIDHARA, Ravi , SAHOTA, Gurkanwal, Singh , BOSSU, Frederic , CHOKSI, Ojas, M.
发明人： ANIRUDDHAN, Sankaran , NARATHONG, Chiewcharn , SRIDHARA, Sriramgopal , SRIDHARA, Ravi , SAHOTA, Gurkanwal, Singh , BOSSU, Frederic , CHOKSI, Ojas, M.
IPC分类号： H03G3/30 , H03D7/16 , H03D7/14
CPC分类号： H03D7/166 , H03D7/1441 , H03D7/1483 , H03D7/165 , H03D2200/0025 , H03G3/3052
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在示例性实施例中，当接收机或发射机以高增益模式工作时，可以增加LO缓冲器和/或混频器大小，而当接收机或发射机以低增益模式工作时，LO缓冲器和/或混频器大小可能会减小。在示例性实施例中，锁定步骤中LO缓冲器和混合器尺寸增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体示例性实施例的电路拓扑和控制方案。

7. 发明申请

WO2022125374A2 SWITCH WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION 审中-公开
公开(公告)号：WO2022125374A2
公开(公告)日：2022-06-16
申请号：PCT/US2021/061600
申请日：2021-12-02
申请人： QUALCOMM INCORPORATED
发明人： HASSAN, Muhammad , ASURI, Bhushan Shanti , DUNWORTH, Jeremy Darren , SRIDHARA, Ravi
IPC分类号： H01L27/02 , H03F1/52 , H03F3/24 , H04B1/44 , H04B1/58 , H01L23/60 , H01L27/0255 , H03F1/523 , H03F2200/318 , H03F2200/441 , H03F2200/451 , H03F2200/541 , H03F3/195 , H03F3/245 , H04B1/581
摘要： According to certain aspects, a chip includes a pad, a power amplifier, a transformer coupled between an output of the power amplifier and the pad, a transistor coupled between the transformer and a ground, and a first clamp circuit coupled between a gate of the transistor and a drain of the transistor.

8. 发明申请

WO2022103551A1 ANTENNA SWITCHING SCHEME 审中-公开
公开(公告)号：WO2022103551A1
公开(公告)日：2022-05-19
申请号：PCT/US2021/055204
申请日：2021-10-15
申请人： QUALCOMM INCORPORATED
发明人： HASSAN, Muhammad , GOLDBLATT, Jeremy , ASURI, Bhushan Shanti , DUNWORTH, Jeremy, Darren , BELLAOUAR, Abdellatif , SRIDHARA, Ravi , GARCIA, Jorge
IPC分类号： H04B1/44
摘要： In some aspects, an apparatus includes a transformer including a first inductor, a second inductor, and a third inductor. The apparatus also includes a power amplifier coupled to the first inductor, a first antenna coupled to a first terminal of the second inductor, a second antenna coupled to a second terminal of the second inductor, a first switch coupled between the first terminal of the second inductor and a ground, a second switch coupled between the second terminal of the second inductor and the ground, and a low-noise amplifier coupled to the third inductor.

9. 发明申请

WO2018136485A1 TECHNIQUES FOR LOW-LOSS MULTI-BAND MULTIPLEXING 审中-公开
公开(公告)号：WO2018136485A1
公开(公告)日：2018-07-26
申请号：PCT/US2018/014001
申请日：2018-01-17
申请人： QUALCOMM INCORPORATED
发明人： PATEL, Chirag Dipak , LEUNG, Lai Kan , JIN, Zhang , MISHRA, Chinmaya , SRIDHARA, Ravi , YOON, Youngchang
IPC分类号： H03H7/46 , H04B1/00
摘要： Various aspects described herein relate to low-loss multi-band multiplexing schemes for a wireless communications system, for example, a 5th Generation (5G) New Radio (NR) system. In an aspect, a multiplexer for multi-band wireless communications comprises at least one tuning component configured to transmit or receive at least one signal within a frequency band that is selected from a plurality of frequency bands. The multiplexer further comprises at least one combining component, communicatively coupled with the at least one tuning component, configured to transmit or receive the at least one signal within the selected frequency band. In an aspect, the at least one tuning component is integrated on a chip and the at least one combining component is not integrated on the chip.

10. 发明申请

WO2022125374A1 SWITCH WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION 审中-公开
公开(公告)号：WO2022125374A1
公开(公告)日：2022-06-16
申请号：PCT/US2021/061600
申请日：2021-12-02
申请人： QUALCOMM INCORPORATED [US]/[US]
发明人： HASSAN, Muhammad , ASURI, Bhushan Shanti , DUNWORTH, Jeremy Darren , SRIDHARA, Ravi
IPC分类号： H01L27/02 , H03F1/52 , H03F3/24 , H04B1/44 , H04B1/58
摘要： According to certain aspects, a chip includes a pad, a power amplifier, a transformer coupled between an output of the power amplifier and the pad, a transistor coupled between the transformer and a ground, and a first clamp circuit coupled between a gate of the transistor and a drain of the transistor.

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