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1. 发明申请

US20120180016A1 Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices 有权
标题翻译：用于多VT设备的双聚合图案化的标准单元架构
公开(公告)号：US20120180016A1
公开(公告)日：2012-07-12
申请号：US13004460
申请日：2011-01-11
申请人： PR Chidambaram , Prayag B. Patel , Foua Vang , Pratyush Kamal , Chock H Gan , Chethan Swamynathan
发明人： PR Chidambaram , Prayag B. Patel , Foua Vang , Pratyush Kamal , Chock H Gan , Chethan Swamynathan
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , H01L27/11807
摘要： An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.
摘要翻译：使用包括具有不同电压阈值的装置的标准单元架构制造的装置可以包括与第一通道长度相关联的第一组折线，其中第一组折线中的每个折线被基本恒定的间距分开。该装置还可以包括与第二通道长度相关联并与第一组折线对准的第二组折线，其中第二组折线中的每条折线被基本恒定的间距横向隔开。该装置还可以包括在第一组折线下方的第一有源区域和第二组折线下方的第二有源区域，其中第一有源区域和第二有源区域被分开小于170nm的距离。

2. 发明授权

US08610176B2 Standard cell architecture using double poly patterning for multi VT devices 有权
标题翻译：标准单元架构，采用双重多晶格形成多VT器件
公开(公告)号：US08610176B2
公开(公告)日：2013-12-17
申请号：US13004460
申请日：2011-01-11
申请人： Prayag B. Patel , Pratyush Kamal , Foua Vang , Chock H. Gan , Pr Chidambaram , Chethan Swamynathan
发明人： Prayag B. Patel , Pratyush Kamal , Foua Vang , Chock H. Gan , Pr Chidambaram , Chethan Swamynathan
IPC分类号： H01L27/00 , H01L21/768
CPC分类号： H01L27/0207 , H01L27/11807
摘要： An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.
摘要翻译：使用包括具有不同电压阈值的装置的标准单元架构制造的装置可以包括与第一通道长度相关联的第一组折线，其中第一组折线中的每个折线被基本恒定的间距分开。该装置还可以包括与第二通道长度相关联并与第一组折线对准的第二组折线，其中第二组折线中的每条折线被基本恒定的间距横向隔开。该装置还可以包括在第一组折线下方的第一有源区域和第二组折线下方的第二有源区域，其中第一有源区域和第二有源区域之间的距离小于170nm。

3. 发明申请

US20130032885A1 AREA EFFICIENT GRIDDED POLYSILICON LAYOUTS 审中-公开
标题翻译：区域有效的多晶硅层
公开(公告)号：US20130032885A1
公开(公告)日：2013-02-07
申请号：US13197195
申请日：2011-08-03
申请人： Chethan Swamynathan , Jay Madhukar Shah , Vijayalakshmi Ranganna , Foua Vang , Pratyush Kamal , Prayag B. Patel
发明人： Chethan Swamynathan , Jay Madhukar Shah , Vijayalakshmi Ranganna , Foua Vang , Pratyush Kamal , Prayag B. Patel
IPC分类号： H01L27/088 , H01L21/02 , H01L21/28
CPC分类号： H01L27/11807 , H01L27/0207
摘要： Gridded polysilicon semiconductor layouts implement double poly patterning to cut polylines of the layout into polyline segments. Devices are arranged on the polyline segments of a common polyline to reduce the area used to implement a circuit structure relative to conventional gridded polysilicon layout. Stacking of PMOS and NMOS devices is enabled by using double poly patterning to implement additional cuts which form additional polyline segments. Metal layer routing may connect nodes of separate polyline segments.
摘要翻译：格栅多晶硅半导体布局实现双重图案化，将布局的折线切割成多段线段。器件布置在公共多段线的多段线段上，以减少相对于常规格栅多晶硅布局实现电路结构的面积。 PMOS和NMOS器件的堆叠可以通过使用双重多晶型来实现额外的切割，形成额外的多段线段。金属层路由可以连接单独多段线段的节点。

4. 发明申请

US20110164808A1 TECHNIQUES PROVIDING FIDUCIAL MARKERS FOR FAILURE ANALYSIS 失效
标题翻译：为失败分析提供FIDUCAL MARKERS的技术
公开(公告)号：US20110164808A1
公开(公告)日：2011-07-07
申请号：US12831541
申请日：2010-07-07
申请人： Michael Laisne , Xiangdong Pan , Foua Vang , Prayag B. Patel , Donald D. Lyons , Martin Villafana
发明人： Michael Laisne , Xiangdong Pan , Foua Vang , Prayag B. Patel , Donald D. Lyons , Martin Villafana
IPC分类号： G06K9/00 , H01L29/06 , H01L21/762
CPC分类号： H01L23/544 , H01L21/6836 , H01L2221/68327 , H01L2221/6834 , H01L2223/54406 , H01L2223/54426 , H01L2223/54473 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.
摘要翻译：半导体管芯包括半导体管芯内的一组间隔元件。间隔单元包括其中的基准标记。基准标记可以位于金属层，扩散层，多晶硅层和/或浅沟槽隔离（STI）结构内。

5. 发明授权

US08420410B2 Techniques providing fiducial markers for failure analysis 失效
标题翻译：为故障分析提供基准标记的技术
公开(公告)号：US08420410B2
公开(公告)日：2013-04-16
申请号：US12831541
申请日：2010-07-07
申请人： Michael Laisne , Xiangdong Pan , Foua Vang , Prayag B. Patel , Donald D. Lyons , Martin Villafana
发明人： Michael Laisne , Xiangdong Pan , Foua Vang , Prayag B. Patel , Donald D. Lyons , Martin Villafana
IPC分类号： H01L21/00
CPC分类号： H01L23/544 , H01L21/6836 , H01L2221/68327 , H01L2221/6834 , H01L2223/54406 , H01L2223/54426 , H01L2223/54473 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.
摘要翻译：半导体管芯包括半导体管芯内的一组间隔元件。间隔单元包括其中的基准标记。基准标记可以位于金属层，扩散层，多晶硅层和/或浅沟槽隔离（STI）结构内。

6. 发明申请

US20120210284A1 Method and Apparatus for Characterizing and Reducing Proximity Effect on Cell Electrical Characteristics 失效
标题翻译：用于表征和减少对电池电气特性的接近效应的方法和装置
公开(公告)号：US20120210284A1
公开(公告)日：2012-08-16
申请号：US13027359
申请日：2011-02-15
申请人： Animesh Datta , Pratyush Kamal , Prayag B. Patel , Xiaonan Zhang
发明人： Animesh Datta , Pratyush Kamal , Prayag B. Patel , Xiaonan Zhang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081 , G06F17/5036
摘要： Circuit elements are characterized for effects of proximity context on electrical characteristic. Based on the characterization, proximity context cell models, and corresponding modeled electrical characteristic values are obtained. Logic cells are characterized and modeled according to the proximity context cell models. Optionally the electrical characteristic can be time delay, leakage, dynamic power, or coupling noise among other parameters.
摘要翻译：电路元件的特征在于接近上下文对电特性的影响。基于表征，获得邻近上下文单元模型和相应的建模电特性值。逻辑单元根据邻近情景单元模型进行表征和建模。可选地，电特性可以是其他参数之间的时间延迟，泄漏，动态功率或耦合噪声。

7. 发明授权

US08584075B2 Method and apparatus for characterizing and reducing proximity effect on cell electrical characteristics 失效
标题翻译：用于表征和减少对电池电特性的接近效应的方法和装置
公开(公告)号：US08584075B2
公开(公告)日：2013-11-12
申请号：US13027359
申请日：2011-02-15
申请人： Animesh Datta , Pratyush Kamal , Prayag B. Patel , Xiaonan Zhang
发明人： Animesh Datta , Pratyush Kamal , Prayag B. Patel , Xiaonan Zhang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： Circuit elements are characterized for effects of proximity context on electrical characteristic. Based on the characterization, proximity context cell models, and corresponding modeled electrical characteristic values are obtained. Logic cells are characterized and modeled according to the proximity context cell models. Optionally the electrical characteristic can be time delay, leakage, dynamic power, or coupling noise among other parameters.
摘要翻译：电路元件的特征在于接近上下文对电特性的影响。基于表征，获得邻近上下文单元模型和相应的建模电特性值。逻辑单元根据邻近情景单元模型进行表征和建模。可选地，电特性可以是其他参数之间的时间延迟，泄漏，动态功率或耦合噪声。

8. 发明申请

US20130007681A1 YIELD BASED FLOP HOLD TIME AND SETUP TIME DEFINITION 有权
标题翻译：基于YIELD的FLOP保持时间和设置时间定义
公开(公告)号：US20130007681A1
公开(公告)日：2013-01-03
申请号：US13172951
申请日：2011-06-30
申请人： Xiaonan Zhang , Xiaoliang Bai , Prayag B. Patel
发明人： Xiaonan Zhang , Xiaoliang Bai , Prayag B. Patel
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/10 , G06F2217/84
摘要： Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the point of failure parameter correlated with a specific value of the process variation. A standard deviation associated with the point of failure parameter is determined. The process variation per the standard deviation is calculated and the timing parameter for the circuit element is defined as a function of the failure parameter, the standard deviation, and the process variation per the standard deviation. A margin factor, which varies with the standard deviation, is optionally applied to the timing parameter. The timing parameter may be one of a setup time or hold time.
摘要翻译：用于基于过程变化来定义电路元件的定时参数的系统和方法，包括确定与定时参数相关联的故障点参数，故障点参数与过程变化的特定值相关。确定与故障点参数相关的标准偏差。计算每个标准差的过程变化，并将电路元件的时序参数定义为故障参数，标准偏差和每个标准偏差的过程变化的函数。随着标准偏差而变化的边际因子可选地应用于定时参数。定时参数可以是设置时间或保持时间之一。

9. 发明授权

US08356263B1 Yield based flop hold time and setup time definition 有权
标题翻译：基于产量的触发器保持时间和设置时间定义
公开(公告)号：US08356263B1
公开(公告)日：2013-01-15
申请号：US13172951
申请日：2011-06-30
申请人： Xiaonan Zhang , Xiaoliang Bai , Prayag B. Patel
发明人： Xiaonan Zhang , Xiaoliang Bai , Prayag B. Patel
IPC分类号： G06F9/455
CPC分类号： G06F17/504 , G06F2217/10 , G06F2217/84
摘要： Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the point of failure parameter correlated with a specific value of the process variation. A standard deviation associated with the point of failure parameter is determined. The process variation per the standard deviation is calculated and the timing parameter for the circuit element is defined as a function of the failure parameter, the standard deviation, and the process variation per the standard deviation. A margin factor, which varies with the standard deviation, is optionally applied to the timing parameter. The timing parameter may be one of a setup time or hold time.
摘要翻译：用于基于过程变化来定义电路元件的定时参数的系统和方法，包括确定与定时参数相关联的故障点参数，故障点参数与过程变化的特定值相关。确定与故障点参数相关的标准偏差。计算每个标准差的过程变化，并将电路元件的时序参数定义为故障参数，标准偏差和每个标准偏差的过程变化的函数。随着标准偏差而变化的边际因子可选地应用于定时参数。定时参数可以是设置时间或保持时间之一。

10. 发明申请

US20100109747A1 Systems and Methods Using Improved Clock Gating Cells 有权
标题翻译：使用改进的时钟门控单元的系统和方法
公开(公告)号：US20100109747A1
公开(公告)日：2010-05-06
申请号：US12261428
申请日：2008-10-30
申请人： Animesh Datta , Martin Saint-Laurent , Varun R. Verma , Prayag B. Patel
发明人： Animesh Datta , Martin Saint-Laurent , Varun R. Verma , Prayag B. Patel
IPC分类号： H03K17/30
CPC分类号： H03K19/0016 , H03K3/356086 , H03K19/0013
摘要： A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitry preventing premature charge or discharge of the output logic circuit input node by the pull-up and/or the pull-down circuit when the clock gating cell is enabled.
摘要翻译：时钟门控单元，包括与输入使能逻辑和输出逻辑电路通信的锁存器，其中所述锁存器包括在所述输出逻辑电路的输入节点处的上拉和/或下拉电路以及防止过早的电路当时钟门控单元使能时，由上拉和/或下拉电路对输出逻辑电路输入节点进行充电或放电。

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