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1. 发明授权

US08610176B2 Standard cell architecture using double poly patterning for multi VT devices 有权
标题翻译：标准单元架构，采用双重多晶格形成多VT器件
公开(公告)号：US08610176B2
公开(公告)日：2013-12-17
申请号：US13004460
申请日：2011-01-11
申请人： Prayag B. Patel , Pratyush Kamal , Foua Vang , Chock H. Gan , Pr Chidambaram , Chethan Swamynathan
发明人： Prayag B. Patel , Pratyush Kamal , Foua Vang , Chock H. Gan , Pr Chidambaram , Chethan Swamynathan
IPC分类号： H01L27/00 , H01L21/768
CPC分类号： H01L27/0207 , H01L27/11807
摘要： An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.
摘要翻译：使用包括具有不同电压阈值的装置的标准单元架构制造的装置可以包括与第一通道长度相关联的第一组折线，其中第一组折线中的每个折线被基本恒定的间距分开。该装置还可以包括与第二通道长度相关联并与第一组折线对准的第二组折线，其中第二组折线中的每条折线被基本恒定的间距横向隔开。该装置还可以包括在第一组折线下方的第一有源区域和第二组折线下方的第二有源区域，其中第一有源区域和第二有源区域之间的距离小于170nm。

2. 发明申请

US20120180016A1 Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices 有权
标题翻译：用于多VT设备的双聚合图案化的标准单元架构
公开(公告)号：US20120180016A1
公开(公告)日：2012-07-12
申请号：US13004460
申请日：2011-01-11
申请人： PR Chidambaram , Prayag B. Patel , Foua Vang , Pratyush Kamal , Chock H Gan , Chethan Swamynathan
发明人： PR Chidambaram , Prayag B. Patel , Foua Vang , Pratyush Kamal , Chock H Gan , Chethan Swamynathan
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , H01L27/11807
摘要： An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.
摘要翻译：使用包括具有不同电压阈值的装置的标准单元架构制造的装置可以包括与第一通道长度相关联的第一组折线，其中第一组折线中的每个折线被基本恒定的间距分开。该装置还可以包括与第二通道长度相关联并与第一组折线对准的第二组折线，其中第二组折线中的每条折线被基本恒定的间距横向隔开。该装置还可以包括在第一组折线下方的第一有源区域和第二组折线下方的第二有源区域，其中第一有源区域和第二有源区域被分开小于170nm的距离。

3. 发明授权

US6027982A Method to form shallow trench isolation structures with improved isolation fill and surface planarity 失效
标题翻译：形成具有改进的隔离填充和表面平面性的浅沟槽隔离结构的方法
公开(公告)号：US6027982A
公开(公告)日：2000-02-22
申请号：US245565
申请日：1999-02-05
申请人： Igor V. Peidous , Vladislav Y. Vassiliev , Chock H. Gan , Guang Ping Hua
发明人： Igor V. Peidous , Vladislav Y. Vassiliev , Chock H. Gan , Guang Ping Hua
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76235 , Y10S148/05
摘要： A method to form shallow trench isolation structures with improved isolation fill and surface planarity is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A thin oxide layer is deposited overlying the silicon nitride layer. An isolation trench is etched through the thin oxide layer, the nitride layer, and the pad oxide layer and into the substrate. The silicon nitride layer exposed within the trench is etched to form a lateral undercut leaving a projection of the thin oxide layer and exposing a portion of the underlying pad oxide layer. The thin oxide layer and the exposed portion of the pad oxide layer are etched away thereby exposing portions of the surface of the substrate. A liner oxide is grown on the exposed portions of the semiconductor substrate within the isolation trench and on the surface of the substrate. A layer of isolation dielectric is deposited overlying the liner oxide and the silicon nitride and filling the isolation trench. The isolation dielectric is polished away stopping at the silicon nitride layer. The remaining silicon nitride etched away. The isolation dielectric and the pad oxide are etched away from the surface of the semiconductor substrate. The fabrication of the integrated circuit device is completed.
摘要翻译：描述了形成具有改进的隔离填充和表面平面性的浅沟槽隔离结构的方法。衬垫氧化物层设置在半导体衬底的表面上。在衬垫氧化物层上沉积氮化硅层。沉积在氮化硅层上的薄氧化层。通过薄氧化物层，氮化物层和焊盘氧化物层蚀刻隔离沟槽并进入衬底。在沟槽内暴露的氮化硅层被蚀刻以形成横向底切，留下薄的氧化物层的突起，并暴露下面的衬垫氧化物层的一部分。薄氧化物层和衬垫氧化物层的暴露部分被蚀刻掉，从而暴露衬底表面的部分。衬垫氧化物生长在半导体衬底在隔离沟槽内和衬底表面上的暴露部分上。沉积覆盖衬垫氧化物和氮化硅并且填充隔离沟槽的隔离电介质层。在氮化硅层处停止隔离电介质被抛光。剩余的氮化硅蚀刻掉。绝缘电介质和衬垫氧化物被蚀刻离开半导体衬底的表面。完成集成电路器件的制造。

4. 发明授权

US5856225A Creation of a self-aligned, ion implanted channel region, after source and drain formation 失效
标题翻译：在源极和漏极形成之后创建自对准的离子注入通道区域
公开(公告)号：US5856225A
公开(公告)日：1999-01-05
申请号：US976941
申请日：1997-11-24
申请人： Teck Koon Lee , Lap Chan , Chock H. Gan , Po-Ching Liu
发明人： Teck Koon Lee , Lap Chan , Chock H. Gan , Po-Ching Liu
IPC分类号： H01L21/28 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66537 , H01L29/66545 , H01L29/6659 , H01L21/28052
摘要： A method of fabricating a MOSFET device, in which a source and drain region has been formed, prior to the formation of an ion implanted channel region, has been developed. The early creation of source and drain region allows a high temperature anneal to be performed, removing damage resulting from the source and drain ion implantation procedures, however without redistribution of channel dopants. The method features creating an opening in an insulator layer, after the source and drain formation, and then forming the channel region in the semiconductor substrate, directly underlying the opening in the insulator layer. A polysilicon gate structure is next formed in the opening, resulting in self-alignment to the underlying channel region.
摘要翻译：已经开发了在形成离子注入沟道区之前制造其中形成源区和漏区的MOSFET器件的方法。源极和漏极区域的早期创建允许执行高温退火，消除源极和漏极离子注入过程造成的损伤，然而不会重新分布沟道掺杂剂。该方法在源极和漏极形成之后在绝缘体层中产生开口，然后在半导体衬底中形成直接位于绝缘体层中的开口下方的沟道区。随后在开口中形成多晶硅栅结构，导致与底层沟道区的自对准。

5. 发明授权

US08558320B2 Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior 有权
标题翻译：采用具有对称电气行为的物理不对称半导体器件的系统和方法
公开(公告)号：US08558320B2
公开(公告)日：2013-10-15
申请号：US12638557
申请日：2009-12-15
申请人： Haining Yang , Chock H. Gan , Zhongze Wang , Beom-Mo Han
发明人： Haining Yang , Chock H. Gan , Zhongze Wang , Beom-Mo Han
IPC分类号： H01L27/092
CPC分类号： H01L27/0207 , H01L21/823425 , H01L21/823475 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.
摘要翻译：一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

6. 发明申请

US20110140288A1 Systems and Methods Employing a Physically Asymmetric Semiconductor Device Having Symmetrical Electrical Behavior 有权
标题翻译：采用具有对称电气行为的物理不对称半导体器件的系统和方法
公开(公告)号：US20110140288A1
公开(公告)日：2011-06-16
申请号：US12638557
申请日：2009-12-15
申请人： Haining Yang , Chock H. Gan , Zhongze Wang , Beom-Mo Han
发明人： Haining Yang , Chock H. Gan , Zhongze Wang , Beom-Mo Han
IPC分类号： H01L23/50 , H01L21/3205
CPC分类号： H01L27/0207 , H01L21/823425 , H01L21/823475 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.
摘要翻译：一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

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