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1. 发明申请

US20100109747A1 Systems and Methods Using Improved Clock Gating Cells 有权
标题翻译：使用改进的时钟门控单元的系统和方法
公开(公告)号：US20100109747A1
公开(公告)日：2010-05-06
申请号：US12261428
申请日：2008-10-30
申请人： Animesh Datta , Martin Saint-Laurent , Varun R. Verma , Prayag B. Patel
发明人： Animesh Datta , Martin Saint-Laurent , Varun R. Verma , Prayag B. Patel
IPC分类号： H03K17/30
CPC分类号： H03K19/0016 , H03K3/356086 , H03K19/0013
摘要： A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitry preventing premature charge or discharge of the output logic circuit input node by the pull-up and/or the pull-down circuit when the clock gating cell is enabled.
摘要翻译：时钟门控单元，包括与输入使能逻辑和输出逻辑电路通信的锁存器，其中所述锁存器包括在所述输出逻辑电路的输入节点处的上拉和/或下拉电路以及防止过早的电路当时钟门控单元使能时，由上拉和/或下拉电路对输出逻辑电路输入节点进行充电或放电。

2. 发明授权

US08030982B2 Systems and methods using improved clock gating cells 有权
标题翻译：使用改进的时钟门控单元的系统和方法
公开(公告)号：US08030982B2
公开(公告)日：2011-10-04
申请号：US12261428
申请日：2008-10-30
申请人： Animesh Datta , Martin Saint-Laurent , Varun Verma , Prayag B. Patel
发明人： Animesh Datta , Martin Saint-Laurent , Varun Verma , Prayag B. Patel
IPC分类号： G06F1/04
CPC分类号： H03K19/0016 , H03K3/356086 , H03K19/0013
摘要： A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitry preventing premature charge or discharge of the output logic circuit input node by the pull-up and/or the pull-down circuit when the clock gating cell is enabled.
摘要翻译：时钟门控单元，包括与输入使能逻辑和输出逻辑电路通信的锁存器，其中所述锁存器包括在所述输出逻辑电路的输入节点处的上拉和/或下拉电路以及防止过早的电路当时钟门控单元使能时，由上拉和/或下拉电路对输出逻辑电路输入节点进行充电或放电。

3. 发明授权

US08584075B2 Method and apparatus for characterizing and reducing proximity effect on cell electrical characteristics 失效
标题翻译：用于表征和减少对电池电特性的接近效应的方法和装置
公开(公告)号：US08584075B2
公开(公告)日：2013-11-12
申请号：US13027359
申请日：2011-02-15
申请人： Animesh Datta , Pratyush Kamal , Prayag B. Patel , Xiaonan Zhang
发明人： Animesh Datta , Pratyush Kamal , Prayag B. Patel , Xiaonan Zhang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： Circuit elements are characterized for effects of proximity context on electrical characteristic. Based on the characterization, proximity context cell models, and corresponding modeled electrical characteristic values are obtained. Logic cells are characterized and modeled according to the proximity context cell models. Optionally the electrical characteristic can be time delay, leakage, dynamic power, or coupling noise among other parameters.
摘要翻译：电路元件的特征在于接近上下文对电特性的影响。基于表征，获得邻近上下文单元模型和相应的建模电特性值。逻辑单元根据邻近情景单元模型进行表征和建模。可选地，电特性可以是其他参数之间的时间延迟，泄漏，动态功率或耦合噪声。

4. 发明申请

US20120210284A1 Method and Apparatus for Characterizing and Reducing Proximity Effect on Cell Electrical Characteristics 失效
标题翻译：用于表征和减少对电池电气特性的接近效应的方法和装置
公开(公告)号：US20120210284A1
公开(公告)日：2012-08-16
申请号：US13027359
申请日：2011-02-15
申请人： Animesh Datta , Pratyush Kamal , Prayag B. Patel , Xiaonan Zhang
发明人： Animesh Datta , Pratyush Kamal , Prayag B. Patel , Xiaonan Zhang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081 , G06F17/5036
摘要： Circuit elements are characterized for effects of proximity context on electrical characteristic. Based on the characterization, proximity context cell models, and corresponding modeled electrical characteristic values are obtained. Logic cells are characterized and modeled according to the proximity context cell models. Optionally the electrical characteristic can be time delay, leakage, dynamic power, or coupling noise among other parameters.
摘要翻译：电路元件的特征在于接近上下文对电特性的影响。基于表征，获得邻近上下文单元模型和相应的建模电特性值。逻辑单元根据邻近情景单元模型进行表征和建模。可选地，电特性可以是其他参数之间的时间延迟，泄漏，动态功率或耦合噪声。

5. 发明授权

US08487658B2 Compact and robust level shifter layout design 有权
标题翻译：紧凑而鲁棒的电平移位器布局设计
公开(公告)号：US08487658B2
公开(公告)日：2013-07-16
申请号：US13180598
申请日：2011-07-12
申请人： Animesh Datta , William James Goodall, III
发明人： Animesh Datta , William James Goodall, III
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H01L27/0207 , H03K19/018521
摘要： Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first N-well and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well.
摘要翻译：用于批量CMOS技术中的电压电平转换器（VLS）设计的方法和装置。一种多电压电路或VLS，可在不同的电压电平下工作，并可为电平移位器设计的多位实现提供面积和功耗。一个两位VLS，用于将位从第一电压电平逻辑移位到第二电压电平逻辑。 VLS在衬底中形成有第一N阱。 VLS在衬底中形成有第二N阱，邻近第一N阱的一侧。 VLS在衬底中形成有第三N阱，邻近第一N阱的一侧并与第二N阱相对。第一单位VLS电路，其具有形成在第一N阱上的部分和形成在第二N阱上的部分。具有形成在第一N阱上的部分和形成在第三N阱上的部分的第二位VLS电路。

6. 发明申请

US20130015882A1 Compact and Robust Level Shifter Layout Design 有权
标题翻译：紧凑和坚固的水平移位器布局设计
公开(公告)号：US20130015882A1
公开(公告)日：2013-01-17
申请号：US13180598
申请日：2011-07-12
申请人： Animesh Datta , William James Goodall, III
发明人： Animesh Datta , William James Goodall, III
IPC分类号： H03K19/0175 , H01L21/82
CPC分类号： H01L27/0207 , H03K19/018521
摘要： Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first N-well and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well.
摘要翻译：用于批量CMOS技术中的电压电平转换器（VLS）设计的方法和装置。一种多电压电路或VLS，可在不同的电压电平下工作，并可为电平移位器设计的多位实现提供面积和功耗。一个两位VLS，用于将位从第一电压电平逻辑移位到第二电压电平逻辑。 VLS在衬底中形成有第一N阱。 VLS在衬底中形成有第二N阱，邻近第一N阱的一侧。 VLS在衬底中形成有第三N阱，邻近第一N阱的一侧并与第二N阱相对。第一单位VLS电路，其具有形成在第一N阱上的部分和形成在第二N阱上的部分。具有形成在第一N阱上的部分和形成在第三N阱上的部分的第二位VLS电路。

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