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1. 发明授权

US09177095B1 Methods, systems, and articles of manufacture for creating or manipulating electrical data sets for an electronic design 有权
标题翻译：用于创建或操纵电子设计的电子数据集的方法，系统和制造
公开(公告)号：US09177095B1
公开(公告)日：2015-11-03
申请号：US13282177
申请日：2011-10-26
申请人： Prakash Krishnan , Wilfred Vance Kenzle , Akshat Shah
发明人： Prakash Krishnan , Wilfred Vance Kenzle , Akshat Shah
IPC分类号： G06G7/62 , G06F17/50
CPC分类号： G06F17/5063 , G06F17/5036 , G06F17/5045 , G06F17/5068 , G06F17/5081
摘要： Disclosed are method(s), system(s), and article(s) of manufacture for creating or manipulating electrical data sets for an electronic design across multiple abstraction levels. The method identifies simulation result(s) obtained from simulation run(s) for an electronic circuit or at least a portion thereof, identifies at least a part of one or more sets of simulation results, each of which is obtained from a simulation run for the electronic circuit or at least a portion thereof at the first abstraction level, identify relevant electrical data or information for design under test instance(s) of a master library or a master cell and creates electrical data set(s), generates a view for at least some of the electrical data set(s), and hand-off the electrical data set(s) to second abstraction level. The method may further identify preexisting electrical data set(s). The method may further compare the electrical data set(s) and preexisting electrical data set(s).
摘要翻译：公开了用于跨多个抽象层次创建或操纵电子设计的电气数据集的方法，系统和制造文章。该方法识别从电子电路或其至少一部分的模拟运行获得的模拟结果，识别一组或多组模拟结果的至少一部分，每组模拟结果是从模拟运行获得的，电子电路或其至少一部分在第一抽象级别识别用于在主库或主单元的测试实例下的设计的相关电数据或信息，并创建电数据集，生成电视数据或视图，电数据集中的至少一些，以及将电数据集切换到第二抽象级。该方法还可以识别预先存在的电数据集。该方法可以进一步比较电数据集和预先存在的电数据集。

2. 发明授权

US08769456B1 Methods, systems, and articles for implementing extraction and electrical analysis-driven module creation 有权
标题翻译：用于实施提取和电气分析驱动模块创建的方法，系统和文章
公开(公告)号：US08769456B1
公开(公告)日：2014-07-01
申请号：US13282426
申请日：2011-10-26
申请人： Prakash Krishnan , Jeremiah Cessna , Akshat Shah , Keith Dennison
发明人： Prakash Krishnan , Jeremiah Cessna , Akshat Shah , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5068 , G06F17/5081
摘要： Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs are thus made electrically aware of such data from the physical domain and may incorporate any layout induced effects early in the schematic design stage or even at the time a schematic instance of a physical module is to be created in the schematic domain.
摘要翻译：这里描述的各种过程或模块使得原理图设计工具能够获得物理设计的物理数据，并且使用这种物理数据在示意性域中执行一个或多个模拟，使得原理图设计工具被电气感知物理数据。可以将物理域中的各种类型的数据传送到原理图领域，以便用传输的数据执行一个或多个示意图模拟。因此，原理图设计使电气感知来自物理领域的这种数据，并且可以在原理图设计阶段的早期甚至在逻辑结构域中创建物理模块的示意性实例的时候可以并入任何布局引起的效应。

3. 发明授权

US08694950B2 Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness 有权
标题翻译：实现具有电气意识的电子电路设计的方法，系统和制造
公开(公告)号：US08694950B2
公开(公告)日：2014-04-08
申请号：US12982721
申请日：2010-12-30
申请人： Michael McSherry , David White , Ed Fischer , Bruce Yanagida , Prakash Gopalakrishnan , Keith Dennison , Akshat Shah
发明人： Michael McSherry , David White , Ed Fischer , Bruce Yanagida , Prakash Gopalakrishnan , Keith Dennison , Akshat Shah
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness.
摘要翻译：公开了一种用于实现具有电气意识的电子电路设计的方法，系统和计算机程序产品。该方法或系统使用电寄生数据或与电寄生相关联的电特性数据来更新原理图级别工具和物理设计工具，因此原理图和物理设计工具都可以了解执行中的电子寄生或特征数据它们的功能如基于抽取的模拟。方法或系统在实现或创建少于完整布局的部分布局时也会意识到EM或IR-drop约束。该方法或系统还提供用于设计工具的用户界面，以提供用于实现具有电气意识的电子电路设计的原位，可定制的实时信息。方法或系统还支持电气电路设计实现的约束验证，具有电气意识。

4. 发明授权

US08762914B2 Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness 有权
标题翻译：用于实现具有电气意识的电子电路设计的约束验证的方法，系统和制造
公开(公告)号：US08762914B2
公开(公告)日：2014-06-24
申请号：US12982732
申请日：2010-12-30
申请人： Ed Fischer , Michael McSherry , David White , Bruce Yanagida , Akshat Shah
发明人： Ed Fischer , Michael McSherry , David White , Bruce Yanagida , Akshat Shah
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied. Some embodiments further map schematic level parasitic constraints to a physical design representation and then compares the mapped parasitic constraints with corresponding electrical constraints to determine whether the mapped constraints are met.
摘要翻译：公开了用于实现具有电气意识的电子电路设计的约束验证的方法，系统和制造。一些实施例识别或设置寄生约束，并将电子寄生与相应的寄生约束进行比较，以确定是否满足寄生约束。一些实施例首先识别，确定或更新部分布局的部件的物理数据，并表征与部件的物理数据相关联的电寄生效应。一些实施例基于示意性模拟结果和性能约束来识别或确定一些示意图级性能约束并且估计寄生约束; 然后将估计的寄生约束与相应的电寄生效应进行比较，以确定是否满足约束。一些实施例还将原理层级寄生约束映射到物理设计表示，然后将映射的寄生约束与对应的电限制进行比较，以确定是否满足映射的约束。

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