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1. 发明授权

US08612921B1 Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy 有权
公开(公告)号：US08612921B1
公开(公告)日：2013-12-17
申请号：US13601635
申请日：2012-08-31
申请人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
发明人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

2. 发明授权

US08584072B1 Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy 有权
标题翻译：在电路设计和使用不同精度模式的寄生感知电路设计中对布局进行建模的技术
公开(公告)号：US08584072B1
公开(公告)日：2013-11-12
申请号：US13601757
申请日：2012-08-31
申请人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
发明人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.
摘要翻译：向用户呈现模拟环境，在该环境中用户被提供用于在不同精度的寄生模拟模式之间进行选择，模式包括不具有寄生效应的模式以及包括具有不同精度的寄生效应的多种模式。从用户接收到各种模式之间的选择，并以选定的准确度进行模拟测试。

3. 发明授权

US08261228B1 Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy 有权
标题翻译：在电路设计和使用不同精度模式的寄生感知电路设计中对布局进行建模的技术
公开(公告)号：US08261228B1
公开(公告)日：2012-09-04
申请号：US12243394
申请日：2008-10-01
申请人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
发明人： Prakash Gopalakrishnan , Rongchang Yan , Akshat H. Shah , David N. Dixon , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Techniques are presented for accounting for parasitics in the automated design of integrated circuits. In one set of techniques, model values for parasitic models are received on a schematic environment from a user, the parasitic models are evaluated from the schematic using the received model values, the parasitic models are transferred to a layout environment, and the transferred parasitic models are evaluated on the layout environment. In other techniques, model values are received for parasitic models from a user, the parasitic models are evaluated on the layout environment, and the process then backannotates the parasitic models evaluated on the layout environment and corresponding parameter values to a schematic environment. In yet other techniques, a user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.
摘要翻译：介绍了在集成电路自动化设计中考虑寄生效应的技术。在一组技术中，在用户的原理图环境中接收寄生模型的模型值，使用接收的模型值从原理图评估寄生模型，寄生模型被传送到布局环境，并且传递的寄生模型在布局环境中进行评估。在其他技术中，接收来自用户的寄生模型的模型值，在布局环境中对寄生模型进行评估，然后该过程将对布局环境评估的寄生模型和相应的参数值反馈到原理图环境。在其它技术中，向用户呈现模拟环境，在该模拟环境中，向用户提供选择以选择不同精度的寄生模拟模式，包括不具有寄生效应的模式，以及多种模式，包括具有不同程度的准确性。从用户接收到各种模式之间的选择，并以选定的准确度进行模拟测试。

4. 发明授权

US08694950B2 Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness 有权
标题翻译：实现具有电气意识的电子电路设计的方法，系统和制造
公开(公告)号：US08694950B2
公开(公告)日：2014-04-08
申请号：US12982721
申请日：2010-12-30
申请人： Michael McSherry , David White , Ed Fischer , Bruce Yanagida , Prakash Gopalakrishnan , Keith Dennison , Akshat Shah
发明人： Michael McSherry , David White , Ed Fischer , Bruce Yanagida , Prakash Gopalakrishnan , Keith Dennison , Akshat Shah
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness.
摘要翻译：公开了一种用于实现具有电气意识的电子电路设计的方法，系统和计算机程序产品。该方法或系统使用电寄生数据或与电寄生相关联的电特性数据来更新原理图级别工具和物理设计工具，因此原理图和物理设计工具都可以了解执行中的电子寄生或特征数据它们的功能如基于抽取的模拟。方法或系统在实现或创建少于完整布局的部分布局时也会意识到EM或IR-drop约束。该方法或系统还提供用于设计工具的用户界面，以提供用于实现具有电气意识的电子电路设计的原位，可定制的实时信息。方法或系统还支持电气电路设计实现的约束验证，具有电气意识。

5. 发明授权

US08694933B2 Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness 有权
标题翻译：用于实现具有仿真意识的电子电路设计的方法，系统和制造
公开(公告)号：US08694933B2
公开(公告)日：2014-04-08
申请号：US12982790
申请日：2010-12-30
申请人： Prakash Gopalakrishnan , Michael McSherry , David White , Ed Fischer , Bruce Yanagida , Keith Dennison
发明人： Prakash Gopalakrishnan , Michael McSherry , David White , Ed Fischer , Bruce Yanagida , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.
摘要翻译：公开了实现具有模拟意识的电子设计的方法，系统和制造。在原理图级别识别或创建和模拟原理图，以表征电路的功能特性或确保电路设计符合要求的设计规范。识别，创建或更新设计组件的物理数据，并对与物理数据相关的电子寄存进行表征。与寄生相关联的一个或多个电特性被进一步表征并映射到仿真器以重新模拟电路设计以分析寄生效应的影响。一些实施例通过接受来自设计环境的增量设计或参数改变以交互方式递增地重新运行相同的模拟过程。

6. 发明授权

US07277804B2 Method and system for performing effective resistance calculation for a network of resistors 有权
标题翻译：用于对电阻网进行有效电阻计算的方法和系统
公开(公告)号：US07277804B2
公开(公告)日：2007-10-02
申请号：US11134803
申请日：2005-05-20
申请人： Ian Gebbie , Ian Dennison , Zsolt Haag , Keith Dennison
发明人： Ian Gebbie , Ian Dennison , Zsolt Haag , Keith Dennison
IPC分类号： G01R25/00 , G06F17/50
CPC分类号： G06F17/5036
摘要： A method, mechanism, and system for determining an effective resistance for a network of resistors, irrespective of the number of terminals is provided. An aspect of an approach relates to the reduction of any network of resistors to a single resistance value. Another aspect of an approach relates to the application of a power loss calculation to determine the effective resistance. Yet another aspect of an approach relates to the integration of the method/mechanism with an analog simulator.
摘要翻译：提供了用于确定电阻网络的有效电阻的方法，机构和系统，而不考虑端子数量。方法的一个方面涉及将电阻器的任何网络减少到单个电阻值。方法的另一方面涉及功率损耗计算的应用以确定有效电阻。方法的另一方面涉及方法/机构与模拟仿真器的集成。

7. 发明授权

US08769456B1 Methods, systems, and articles for implementing extraction and electrical analysis-driven module creation 有权
标题翻译：用于实施提取和电气分析驱动模块创建的方法，系统和文章
公开(公告)号：US08769456B1
公开(公告)日：2014-07-01
申请号：US13282426
申请日：2011-10-26
申请人： Prakash Krishnan , Jeremiah Cessna , Akshat Shah , Keith Dennison
发明人： Prakash Krishnan , Jeremiah Cessna , Akshat Shah , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5068 , G06F17/5081
摘要： Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs are thus made electrically aware of such data from the physical domain and may incorporate any layout induced effects early in the schematic design stage or even at the time a schematic instance of a physical module is to be created in the schematic domain.
摘要翻译：这里描述的各种过程或模块使得原理图设计工具能够获得物理设计的物理数据，并且使用这种物理数据在示意性域中执行一个或多个模拟，使得原理图设计工具被电气感知物理数据。可以将物理域中的各种类型的数据传送到原理图领域，以便用传输的数据执行一个或多个示意图模拟。因此，原理图设计使电气感知来自物理领域的这种数据，并且可以在原理图设计阶段的早期甚至在逻辑结构域中创建物理模块的示意性实例的时候可以并入任何布局引起的效应。

8. 发明申请

US20050288914A1 Method and system for performing effective resistance calculation for a network of resistors 有权
标题翻译：用于对电阻网进行有效电阻计算的方法和系统
公开(公告)号：US20050288914A1
公开(公告)日：2005-12-29
申请号：US11134803
申请日：2005-05-20
申请人： Ian Gebbie , Ian Dennison , Zsolt Haag , Keith Dennison
发明人： Ian Gebbie , Ian Dennison , Zsolt Haag , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method, mechanism, and system for determining an effective resistance for a network of resistors, irrespective of the number of terminals is provided. An aspect of an approach relates to the reduction of any network of resistors to a single resistance value. Another aspect of an approach relates to the application of a power loss calculation to determine the effective resistance. Yet another aspect of an approach relates to the integration of the method/mechanism with an analog simulator.
摘要翻译：提供了用于确定电阻网络的有效电阻的方法，机构和系统，而不考虑端子数量。方法的一个方面涉及将电阻器的任何网络减少到单个电阻值。方法的另一方面涉及功率损耗计算的应用以确定有效电阻。方法的另一方面涉及方法/机构与模拟仿真器的集成。

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