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1. 发明申请

US20120056259A1 MEMORY CELL, MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY CELL 有权
标题翻译：存储器单元，存储器件和用于制造存储器单元的方法
公开(公告)号：US20120056259A1
公开(公告)日：2012-03-08
申请号：US12877284
申请日：2010-09-08
申请人： Po-Chou Chen , Yao-Wen Chang , I-Chen Yang
发明人： Po-Chou Chen , Yao-Wen Chang , I-Chen Yang
IPC分类号： H01L29/68 , H01L21/762
CPC分类号： H01L21/76232 , H01L27/11568 , H01L29/792
摘要： A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region.
摘要翻译：提供了包括基板，堆叠栅极结构和第一隔离结构的存储单元。衬底具有位于第一掺杂区域和第二掺杂区域之间的第一掺杂区域，第二掺杂区域和沟道区域。堆叠的栅极结构设置在沟道上，并且至少包括电荷捕获层和从底部到顶部的栅极。第一隔离结构设置在衬底中并连接到第一掺杂区并从第一掺杂区向下延伸预定长度，第一隔离结构的底部低于第一掺杂区的底部。

2. 发明授权

US08014203B2 Memory device and methods for fabricating and operating the same 有权
标题翻译：存储器件及其制造和操作的方法
公开(公告)号：US08014203B2
公开(公告)日：2011-09-06
申请号：US12614647
申请日：2009-11-09
申请人： I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu , Guan-Wei Wu , Tao-Yuan Lin , Po-Chou Chen
发明人： I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu , Guan-Wei Wu , Tao-Yuan Lin , Po-Chou Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , H01L27/11568 , H01L29/42352 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.
摘要翻译：描述了存储器件，其包括衬底，导电层，多个电荷存储层和多个掺杂区域。衬底具有形成在其中的多个沟槽。导电层设置在基板上并填充沟槽。电荷存储层分别设置在沟槽中的衬底和导电层之间，其中电荷存储层彼此分离。掺杂区域分别配置在沟槽底部的衬底中。

3. 发明申请

US20100302855A1 MEMORY DEVICE AND METHODS FOR FABRICATING AND OPERATING THE SAME 有权
标题翻译：存储器件及其制造和操作的方法
公开(公告)号：US20100302855A1
公开(公告)日：2010-12-02
申请号：US12614647
申请日：2009-11-09
申请人： I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu , Guan-Wei Wu , Tao-Yuan Lin , Po-Chou Chen
发明人： I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu , Guan-Wei Wu , Tao-Yuan Lin , Po-Chou Chen
IPC分类号： G11C16/04 , H01L29/792 , H01L21/336
CPC分类号： G11C16/0475 , H01L27/11568 , H01L29/42352 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.
摘要翻译：描述了存储器件，其包括衬底，导电层，多个电荷存储层和多个掺杂区域。衬底具有形成在其中的多个沟槽。导电层设置在基板上并填充沟槽。电荷存储层分别设置在沟槽中的衬底和导电层之间，其中电荷存储层彼此分离。掺杂区域分别配置在沟槽底部的衬底中。

4. 发明授权

US08476694B2 Memory cell, memory device and method for manufacturing memory cell 有权
标题翻译：存储单元，存储器件和用于制造存储单元的方法
公开(公告)号：US08476694B2
公开(公告)日：2013-07-02
申请号：US12877284
申请日：2010-09-08
申请人： Po-Chou Chen , Yao-Wen Chang , I-Chen Yang
发明人： Po-Chou Chen , Yao-Wen Chang , I-Chen Yang
IPC分类号： H01L29/788
CPC分类号： H01L21/76232 , H01L27/11568 , H01L29/792
摘要： A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region.
摘要翻译：提供了包括基板，堆叠栅极结构和第一隔离结构的存储单元。衬底具有位于第一掺杂区域和第二掺杂区域之间的第一掺杂区域，第二掺杂区域和沟道区域。堆叠的栅极结构设置在沟道上，并且至少包括电荷捕获层和从底部到顶部的栅极。第一隔离结构设置在衬底中并连接到第一掺杂区并从第一掺杂区向下延伸预定长度，第一隔离结构的底部低于第一掺杂区的底部。

5. 发明申请

US20120140556A1 METHOD OF OPERATING FLASH MEMORY 审中-公开
标题翻译：操作闪存的方法
公开(公告)号：US20120140556A1
公开(公告)日：2012-06-07
申请号：US12961847
申请日：2010-12-07
申请人： PO-CHOU CHEN , Tao-Cheng Lu , Yao-Wen Chang , I-Chen Yang
发明人： PO-CHOU CHEN , Tao-Cheng Lu , Yao-Wen Chang , I-Chen Yang
IPC分类号： G11C16/04 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： A method of operating a flash memory is described. When a first storage site has 2n program levels, the numbers of program levels of the storage sites neighboring to the first storage site are set to be 2n-1. When a second storage site has 2n-1 program levels, the numbers of program levels of the storage sites neighboring to the second storage site are set to be 2n. Each program level corresponds to a different Vt-distribution.
摘要翻译：描述了一种操作闪速存储器的方法。当第一存储站点具有2n个程序级时，与第一存储站点相邻的存储站点的程序级数被设置为2n-1。当第二存储站点具有2n-1个程序级时，与第二存储站点相邻的存储站点的程序级数被设置为2n。每个节目级别对应于不同的Vt分布。

6. 发明授权

US08072803B2 Memory device and methods for fabricating and operating the same 有权
标题翻译：存储器件及其制造和操作的方法
公开(公告)号：US08072803B2
公开(公告)日：2011-12-06
申请号：US12471660
申请日：2009-05-26
申请人： I-Chen Yang , Guan-Wei Wu , Po-Chou Chen , Yao-Wen Chang , Tao-Cheng Lu
发明人： I-Chen Yang , Guan-Wei Wu , Po-Chou Chen , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , H01L27/11521 , H01L27/11568
摘要： The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first doped regions are configured in the substrate adjacent to both sides of an upper portion of each trench, respectively. The first doped regions between the neighbouring trenches are separated from each other. The second doped regions are configured in the substrate under bottoms of the trenches, respectively. The second doped regions and the first doped regions are separated from each other, such that each memory cell includes six physical bits.
摘要翻译：描述了存储器件，其包括衬底，导电层，电荷存储层，多个第一掺杂区域和多个第二掺杂区域。衬底具有形成在其中的多个沟槽。导电层设置在基板上并填充沟槽。电荷存储层设置在基板和导电层之间。第一掺杂区域分别配置在与每个沟槽的上部的两侧相邻的衬底中。相邻沟槽之间的第一掺杂区域彼此分离。第二掺杂区分别配置在沟槽底部的衬底中。第二掺杂区域和第一掺杂区域彼此分离，使得每个存储器单元包括六个物理位。

7. 发明申请

US20100112797A1 METHOD FOR FORMING A MEMORY ARRAY 有权
标题翻译：形成记忆阵列的方法
公开(公告)号：US20100112797A1
公开(公告)日：2010-05-06
申请号：US12263091
申请日：2008-10-31
申请人： I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
发明人： I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L21/3205
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/4234 , Y10S438/954
摘要： The invention is directed to a method for forming a memory array. The method comprises steps of providing a substrate having a charge trapping structure formed thereon. A patterned material layer is formed over the substrate and the patterned material layer having a plurality of trenches expose a portion of the charge trapping structure. Furthermore, a plurality of conductive spacers are formed on the sidewalls of the trenches of the patterned material layer respectively and a portion of the charge trapping structure at the bottom of the trenches is exposed by the conductive spacers. An insulating layer is formed over the substrate to fill up the trenches of the patterned material layer. Moreover, a planarization process is performed to remove a portion of the insulating layer until a top surface of the patterned material layer and a top surface of each of the conductive spacers are exposed.
摘要翻译：本发明涉及一种用于形成存储器阵列的方法。该方法包括提供其上形成有电荷捕获结构的衬底的步骤。图案化的材料层形成在衬底上，并且具有多个沟槽的图案化材料层暴露电荷俘获结构的一部分。此外，在图案化材料层的沟槽的侧壁上分别形成多个导电间隔物，并且沟槽底部的电荷捕获结构的一部分被导电间隔物暴露。在衬底上形成绝缘层以填充图案化材料层的沟槽。此外，执行平面化处理以去除绝缘层的一部分，直到图案化材料层的顶表面和每个导电间隔物的顶表面露出。

8. 发明申请

US20090180332A1 OPERATION METHOD OF NITRIDE-BASED FLASH MEMORY AND METHOD OF REDUCING COUPLING INTERFERENCE 有权
标题翻译：基于氮化物的闪存的操作方法和减少耦合干扰的方法
公开(公告)号：US20090180332A1
公开(公告)日：2009-07-16
申请号：US12167464
申请日：2008-07-03
申请人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang
发明人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C16/10
摘要： A method for operating a nitride-based flash memory is provided. The operation method includes pre-performing an interference reduction operation (IRO) before the routine programming operating step. Through bias arrangement of the target memory cell, charges are injected into the charge trapping layer mainly above the junction regions of the memory cell before programming so as to reset the influences caused by coupling interference issues. The operation method of this present invention not only reduces coupling interference but also afford a wider operation window.
摘要翻译：提供了一种用于操作基于氮化物的闪速存储器的方法。操作方法包括在例程编程操作步骤之前预执行干扰减少操作（IRO）。通过目标存储单元的偏置布置，在编程之前，电荷主要在存储单元的结区上方注入到电荷捕获层中，以便复位由耦合干扰问题引起的影响。本发明的操作方法不仅减少了耦合干扰，而且提供了更宽的操作窗口。

9. 发明授权

US08952484B2 Non-volatile memory having isolation structures in and above a substrate and manufacturing method thereof 有权
标题翻译：在基板中和上方具有隔离结构的非易失性存储器及其制造方法
公开(公告)号：US08952484B2
公开(公告)日：2015-02-10
申请号：US12949092
申请日：2010-11-18
申请人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
发明人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L21/70 , H01L29/788 , H01L29/792 , H01L21/8238 , H01L21/336 , H01L21/762
CPC分类号： H01L29/792 , H01L21/76232
摘要： A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.
摘要翻译：提供了一种非易失性存储器及其制造方法。非挥发性存储器包括衬底，栅极结构，第一掺杂区，第二掺杂区和一对隔离结构。栅极结构设置在基板上。栅极结构包括电荷存储结构，栅极和间隔物。电荷存储结构设置在基板上。栅极设置在电荷存储结构上。间隔件设置在栅极和电荷存储结构的侧壁上。第一掺杂区域和第二掺杂区域分别设置在电荷存储结构的两侧的基板中，并且至少位于间隔物之下。隔离结构分别设置在栅极结构的两侧的基板中。

10. 发明申请

US20110182123A1 FLASH MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 有权
标题翻译：闪存及其制造方法及其工作方法
公开(公告)号：US20110182123A1
公开(公告)日：2011-07-28
申请号：US12834228
申请日：2010-07-12
申请人： GUAN-WEI WU , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
发明人： GUAN-WEI WU , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： G11C16/04 , H01L29/792 , H01L21/336 , H01L29/78 , G11C16/16
CPC分类号： H01L29/792 , G11C16/0475 , H01L29/4234 , H01L29/42352
摘要： A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion.
摘要翻译：提供闪速存储器及其制造方法及其操作方法。闪速存储器包括衬底，电荷俘获结构，第一栅极，第二栅极，第三栅极，第一掺杂区域和第二掺杂区域。基板具有突起部。电荷捕获结构设置在衬底上。第一栅极和第二栅极分别设置在突出部分的两侧的电荷捕获结构的上方。第一栅极和第二栅极的顶表面比位于突起部分顶部的电荷捕获结构的顶表面低。第三栅极设置在位于突起部分的顶部上的电荷捕获结构之上。第一掺杂区域和第二掺杂区域分别设置在基板的突出部分的两侧。

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