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1. 发明授权

US08338880B2 Flash memory 有权
标题翻译：闪存
公开(公告)号：US08338880B2
公开(公告)日：2012-12-25
申请号：US12834228
申请日：2010-07-12
申请人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
发明人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L29/66 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , G11C16/0475 , H01L29/4234 , H01L29/42352
摘要： A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion.
摘要翻译：提供闪速存储器及其制造方法及其操作方法。闪速存储器包括衬底，电荷俘获结构，第一栅极，第二栅极，第三栅极，第一掺杂区域和第二掺杂区域。基板具有突起部。电荷捕获结构设置在衬底上。第一栅极和第二栅极分别设置在突出部分的两侧的电荷捕获结构的上方。第一栅极和第二栅极的顶表面比位于突起部分顶部的电荷捕获结构的顶表面低。第三栅极设置在位于突起部分的顶部上的电荷捕获结构之上。第一掺杂区域和第二掺杂区域分别设置在基板的突出部分的两侧。

2. 发明申请

US20080044771A1 Manufacturing method of fuel cell having micro sensors and polymer layers 有权
标题翻译：具有微传感器和聚合物层的燃料电池的制造方法
公开(公告)号：US20080044771A1
公开(公告)日：2008-02-21
申请号：US11826209
申请日：2007-07-13
申请人： Chi-Yuan Lee , Shuo-Jen Lee , Guan-Wei Wu
发明人： Chi-Yuan Lee , Shuo-Jen Lee , Guan-Wei Wu
IPC分类号： H01M8/00 , G03C5/00
CPC分类号： H01M8/04313 , H01M8/0269 , H01M8/04067 , H01M8/04082 , H01M8/04365 , H01M8/04492 , H01M8/1097 , Y02P70/56
摘要： A manufacturing method of fuel cell having micro sensors and polymer layers is disclosed. It include the following steps of: (1) depositing first polymer layer step, (2) first lithographic processing step, (3) depositing chromium layer step, (4) depositing gold layer step, (5) removing first photo-resist layer step, (6) depositing second polymer layer step, (7) second lithographic processing step, (8) plasma etching step, (9) removing second photo-resist layer step, and (10) complete step. About this invention, the polymer layers can protect the micro sensors. The micro sensors can be installed at a specific location in the flow channel. The entire manufacturing cost is lowered.
摘要翻译：公开了具有微传感器和聚合物层的燃料电池的制造方法。它包括以下步骤：（1）沉积第一聚合物层步骤，（2）第一平版印刷加工步骤，（3）沉积铬层步骤，（4）沉积金层步骤，（5）除去第一光刻胶层步骤（6）沉积第二聚合物层步骤，（7）第二光刻处理步骤，（8）等离子体蚀刻步骤，（9）除去第二光刻胶层步骤，（10）完成步骤。关于本发明，聚合物层可保护微传感器。微型传感器可以安装在流道中的特定位置。整个制造成本降低。

3. 发明授权

US08014203B2 Memory device and methods for fabricating and operating the same 有权
标题翻译：存储器件及其制造和操作的方法
公开(公告)号：US08014203B2
公开(公告)日：2011-09-06
申请号：US12614647
申请日：2009-11-09
申请人： I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu , Guan-Wei Wu , Tao-Yuan Lin , Po-Chou Chen
发明人： I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu , Guan-Wei Wu , Tao-Yuan Lin , Po-Chou Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , H01L27/11568 , H01L29/42352 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.
摘要翻译：描述了存储器件，其包括衬底，导电层，多个电荷存储层和多个掺杂区域。衬底具有形成在其中的多个沟槽。导电层设置在基板上并填充沟槽。电荷存储层分别设置在沟槽中的衬底和导电层之间，其中电荷存储层彼此分离。掺杂区域分别配置在沟槽底部的衬底中。

4. 发明授权

US07846398B2 Micro reactor having micro flow-guiding blocks 有权
标题翻译：具有微流导向块的微反应器
公开(公告)号：US07846398B2
公开(公告)日：2010-12-07
申请号：US11896501
申请日：2007-09-04
申请人： Chi-Yuan Lee , Shuo-Jen Lee , Chin-Hua Wu , Guan-Wei Wu
发明人： Chi-Yuan Lee , Shuo-Jen Lee , Chin-Hua Wu , Guan-Wei Wu
IPC分类号： B01J19/00
CPC分类号： B01J19/0093 , B01F5/061 , B01F5/0646 , B01F5/0647 , B01F5/0654 , B01F13/0059 , B01F2005/0621 , B01F2005/0636 , B01J2219/00783 , B01J2219/00835 , B01J2219/00889 , C01B3/323 , C01B2203/0233 , C01B2203/1076 , C01B2203/1082 , C01B2203/1223
摘要： A micro reactor having micro flow-guiding blocks includes a first gas flow channel, a second gas flow channel and a catalytic converter. There are several flow-guiding portions disposed on the first gas flow channel. Each flow-guiding portion has micro flow-guiding blocks, flow-impact recesses, and catalytic portions. The function of the micro flow-guiding block is to guide a flowing direction of the flow toward the catalytic portion on the flow-impact recess in order to increase a possibility of contacting and chemical reaction with the catalytic portion. So, guiding the flow direction toward the catalytic portion can increase the overall reaction efficiency. More turbulence is generated to obtain a better mixing. Plus, its structure is simple.
摘要翻译：具有微流导向块的微反应器包括第一气流通道，第二气流通道和催化转化器。在第一气体流动通道上设置有多个流动引导部。每个导流部分都具有微小的导流块，流动冲击凹槽和催化部分。微流导向块的功能是将流动方向引向流动冲击凹槽上的催化部分，以增加与催化部分接触和化学反应的可能性。因此，引导朝向催化部分的流动方向可以提高整个反应效率。产生更多的湍流以获得更好的混合。另外，它的结构很简单。

5. 发明申请

US20090180332A1 OPERATION METHOD OF NITRIDE-BASED FLASH MEMORY AND METHOD OF REDUCING COUPLING INTERFERENCE 有权
标题翻译：基于氮化物的闪存的操作方法和减少耦合干扰的方法
公开(公告)号：US20090180332A1
公开(公告)日：2009-07-16
申请号：US12167464
申请日：2008-07-03
申请人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang
发明人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C16/10
摘要： A method for operating a nitride-based flash memory is provided. The operation method includes pre-performing an interference reduction operation (IRO) before the routine programming operating step. Through bias arrangement of the target memory cell, charges are injected into the charge trapping layer mainly above the junction regions of the memory cell before programming so as to reset the influences caused by coupling interference issues. The operation method of this present invention not only reduces coupling interference but also afford a wider operation window.
摘要翻译：提供了一种用于操作基于氮化物的闪速存储器的方法。操作方法包括在例程编程操作步骤之前预执行干扰减少操作（IRO）。通过目标存储单元的偏置布置，在编程之前，电荷主要在存储单元的结区上方注入到电荷捕获层中，以便复位由耦合干扰问题引起的影响。本发明的操作方法不仅减少了耦合干扰，而且提供了更宽的操作窗口。

6. 发明申请

US20080266966A1 OPERATION METHOD OF NON-VOLATILE MEMORY AND METHOD OF IMPROVING COUPLING INTERFERENCE FROM NITRIDE-BASED MEMORY 有权
标题翻译：非易失性存储器的操作方法和改进基于氮化物存储器的耦合干扰的方法
公开(公告)号：US20080266966A1
公开(公告)日：2008-10-30
申请号：US11782149
申请日：2007-07-24
申请人： Yao-Wen Chang , Guan-Wei Wu , Tao-Cheng Lu
发明人： Yao-Wen Chang , Guan-Wei Wu , Tao-Cheng Lu
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , G11C16/26
摘要： An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window.
摘要翻译：提供了一种非易失性存储器的操作方法。操作方法是对所选择的基于氮化物的存储单元执行读取操作，将第一正电压施加到与所选存储单元的一侧相邻的字线，并且将第二正电压施加到相邻的另一个字线到所选存储单元的另一侧。本发明的操作方法不仅可以减少耦合干扰问题，而且可以获得更宽的操作窗口。

7. 发明申请

US20120127795A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF AND OPERATING METHOD OF MEMORY CELL 有权
标题翻译：非易失性存储器及其制造方法及其存储单元的操作方法
公开(公告)号：US20120127795A1
公开(公告)日：2012-05-24
申请号：US12949076
申请日：2010-11-18
申请人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
发明人： Guan-Wei Wu , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： G11C16/04 , H01L21/336 , H01L29/792
CPC分类号： H01L21/28282 , G11C16/0475 , H01L27/11565 , H01L27/11568 , H01L29/7923
摘要： A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell.
摘要翻译：提供一种非易失性存储器及其制造方法以及操作存储单元的方法。非易失性存储器包括衬底，第一和第二掺杂区域，带电捕获结构，第一和第二栅极以及栅极间绝缘层。第一和第二掺杂区域设置在衬底中并沿着第一方向延伸。第一和第二掺杂区交替布置。带电捕获结构设置在基板上。第一和第二栅极设置在带电捕获结构上。每个第一栅极位于第一掺杂区域之上。第二栅极沿着第二方向延伸并且位于第二掺杂区域之上。栅间绝缘层设置在第一栅极和第二栅极之间。相邻的第一和第二掺杂区域和第一栅极，其间的第二栅极和带电捕获结构限定了存储单元。

8. 发明申请

US20120126307A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20120126307A1
公开(公告)日：2012-05-24
申请号：US12949092
申请日：2010-11-18
申请人： GUAN-WEI WU , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
发明人： GUAN-WEI WU , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/76232
摘要： A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers.The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.
摘要翻译：提供了一种非易失性存储器及其制造方法。非易失性存储器包括衬底，栅极结构，第一掺杂区，第二掺杂区和一对隔离结构。栅极结构设置在基板上。栅极结构包括电荷存储结构，栅极和间隔物。电荷存储结构设置在基板上。栅极设置在电荷存储结构上。间隔件设置在栅极和电荷存储结构的侧壁上。第一掺杂区域和第二掺杂区域分别设置在电荷存储结构的两侧的基板中，并且至少位于间隔物之下。隔离结构分别设置在栅极结构的两侧的基板中。

9. 发明授权

US08093665B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08093665B2
公开(公告)日：2012-01-10
申请号：US12467479
申请日：2009-05-18
申请人： I-Chen Yang , Guan-Wei Wu , Yao-Wen Chang , Tao-Cheng Lu
发明人： I-Chen Yang , Guan-Wei Wu , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/66636 , H01L29/665 , H01L29/7834
摘要： A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.
摘要翻译：描述了一种半导体器件，其包括衬底，栅极结构，掺杂区域和轻掺杂区域。基板具有阶梯状的上表面，其包括第一表面，第二表面和第三表面。第二表面低于第一表面。第三表面连接第一表面和第二表面。栅极结构设置在第一表面上。掺杂区域在栅极结构的两侧和第二表面的下方在衬底中配置。轻掺杂区域分别配置在栅极结构和掺杂区域之间的衬底中。每个轻掺杂区域包括彼此连接的第一部分和第二部分。第一部分设置在第二表面下方，第二部分设置在第三表面下。

10. 发明申请

US20110080784A1 NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF 有权
标题翻译：非易失性存储器及其操作方法
公开(公告)号：US20110080784A1
公开(公告)日：2011-04-07
申请号：US12574093
申请日：2009-10-06
申请人： Yao-Wen Chang , Guan-Wei Wu , Tao-Cheng Lu
发明人： Yao-Wen Chang , Guan-Wei Wu , Tao-Cheng Lu
IPC分类号： G11C16/04 , G11C16/34 , G11C16/26 , G11C16/10
CPC分类号： G11C16/3468 , G11C16/0466 , G11C16/10
摘要： An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1st level and an auxiliary level respectively according to the 1st threshold-voltage distribution curve and a threshold-voltage auxiliary curve when the first and the second storage positions are programmed to the 1st and Nth levels; and programming the first and the second storage positions to the ith level according to the ith threshold-voltage distribution curve when the first and the second storage positions are not to be programmed to the 1st and Nth levels, wherein i is an integer and 1≦i≦N.
摘要翻译：提供适用于具有第一存储位置和第二存储位置的多级单元的非易失性存储器的操作方法。操作方法包括：设置N个阈值电压分布曲线，其中N个阈值电压分布曲线对应于N个电平，N是大于2的整数; 当第一和第二存储位置被编程到第1和第N级时，根据第一阈值电压分布曲线和阈值电压辅助曲线分别将第一和第二存储位置编程到第一级和辅助级; 以及当所述第一和第二存储位置不被编程到所述第一和第N电平时，根据所述第i阈值电压分布曲线将所述第一和第二存储位置编程为第i级，其中i是整数和1＆nlE; 我＆nlE; N。

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