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    • 5. 发明授权
    • Parallel arranged power supplies
    • 并联电源
    • US07808225B2
    • 2010-10-05
    • US11547416
    • 2005-03-24
    • Ralf BurdenskiPieter Gerrit BlankenGiuseppe GrilloDerk Reefman
    • Ralf BurdenskiPieter Gerrit BlankenGiuseppe GrilloDerk Reefman
    • G05F1/445
    • H02M3/1584Y10T307/50
    • A power supply system comprises a parallel arrangement of a first switched mode power supply (1) which has a first system bandwidth (LB 1) and a second switched mode power supply (2) which has a second system bandwidth (LB2) covering higher frequencies than the first system bandwidth (LB 1). The first switched mode power supply (1) is dimensioned to supply a first maximal output power (P1m), the second switched mode power supply (2) is dimensioned to supply a second maximal output power (P2m) being smaller than the first maximal output power (P1m). A control circuit (3) varies a reference voltage (Vr) of both the first switched mode power supply (1) and the second switched mode power supply (2) to obtain a corresponding variation of an output voltage (Vout) of the parallel arrangement.
    • 电源系统包括具有第一系统带宽(LB1)和第二开关模式电源(2)的第一开关模式电源(1)的并联布置,所述第一开关模式电源具有覆盖较高频率的第二系统带宽(LB2) 比第一个系统带宽(LB 1)。 第一开关模式电源(1)的尺寸设定为提供第一最大输出功率(P1m),第二开关模式电源(2)的尺寸被设计成提供小于第一最大输出功率的第二最大输出功率(P2m) 功率(P1m)。 控制电路(3)改变第一开关模式电源(1)和第二开关模式电源(2)两者的参考电压(Vr),以获得并联装置的输出电压(Vout)的相应变化 。
    • 8. 发明授权
    • Common mode voltage generation at a differential output of an amplifier
    • 在放大器的差分输出端产生共模电压
    • US06987421B2
    • 2006-01-17
    • US10828063
    • 2004-04-20
    • Pieter Gerrit Blanken
    • Pieter Gerrit Blanken
    • H03F3/45H03K19/0175
    • H03F3/45192H03F2203/45398H03F2203/45401
    • A common mode voltage generating circuit has a first and a second output terminal (O1, O2) to supply a common mode voltage (Vcm) to a differential output of an amplifier stage (AMP). A first FET (T1) and a second FET (T2) have interconnected drains, and both have a source coupled to a supply terminal (Vss). A third FET (T3) has a source coupled to the drain of T1, a drain coupled to O1 and to a gate of T1. A fourth FET (T4) has a source coupled to a drain of T2, a drain coupled to O2 and to a gate of T2. A fifth FET (T5) has a gate for receiving a first reference voltage (VI), and a sixth FET (T6) has a source coupled to the drain of T5, a drain receiving a current (2I) from a current source (CS4), wherein the drain and the gate of T6 are interconnected. T3, T4 and T6 have interconnected gates and are biased to operate in their saturation region. T1, T2 and T5 are biased to operate in their linear regions. The common mode voltage generating circuit further comprises a seventh FET (T7) with a source coupled to Vss, a drain coupled to the drain of T5, and with a gate which receives a second reference voltage (Vh). T7 is biased to operate in its linear region. Bipolar transistors may be used instead of FET's.
    • 共模电压发生电路具有第一和第二输出端(O 1,O 2),以向放大器级(AMP)的差分输出端提供共模电压(Vcm)。 第一FET(T 1)和第二FET(T 2)具有互连的漏极,并且它们都具有耦合到电源端子(Vss)的源极。 第三FET(T 3)具有耦合到T 1的漏极的源极,耦合到O 1的漏极和T 1的栅极。 第四FET(T 4)具有耦合到T 2的漏极的源极,耦合到O 2的漏极和T 2的栅极。 第五FET(T 5)具有用于接收第一参考电压(VI)的栅极,并且第六FET(T6)具有耦合到T 5的漏极的源极,从第一FET接收电流(2I)的漏极 电流源(CS 4),其中T 6的漏极和栅极互连。 T 3,T 4和T 6具有互连的栅极并被偏置以在其饱和区域中操作。 T 1,T 2和T 5被偏置以在其线性区域中操作。 共模电压产生电路还包括具有耦合到Vss的源极的第七FET(T 7),耦合到T 5的漏极的漏极和接收第二参考电压(Vh)的栅极。 T 7被偏置以在其线性区域中操作。 可以使用双极晶体管代替FET。