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1. 发明授权

US5345576A Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss 失效
标题翻译：微处理器同时通过外部高速缓存总线和内部高速缓存访问外部缓存，取消内部高速缓存命中的外部高速缓存访问，并通过外部缓存未命中的主存储器总线重新发出访问
公开(公告)号：US5345576A
公开(公告)日：1994-09-06
申请号：US816603
申请日：1991-12-31
申请人： Phillip G. Lee , Eileen Riggs , Gurbir Singh , Randy Steck
发明人： Phillip G. Lee , Eileen Riggs , Gurbir Singh , Randy Steck
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0884 , G06F12/0897
摘要： A data processing system which includes a microprocessor fabricated on an integrated circuit chip, a main memory external to the integrated circuit chip, and a backside cache external to the integrated circuit chip. The backside cache includes a directory RAM for storing cache address tag and encoded cache state bits. A first bus connects the microprocessor to the cache, the first bus including backside bus cache directory tags signals comprised of address bits used for a cache hit comparison in the directory RAM and backside bus cache directory state bits for determining a state encoding of a set in the directory RAM. A second bus connects the microprocessor to the main memory. The directory includes means for comparing the cache directory tags on the first bus with the tags stored in the directory and for asserting a Bmiss signal upon the condition that the directory tag stored in the backside bus cache directory do not match the backside bus cache directory tags signals. The microprocessor responds to the Bmiss signal by issuing the access onto the second bus in the event of a cache miss.
摘要翻译：一种数据处理系统，包括在集成电路芯片上制造的微处理器，集成电路芯片外部的主存储器和集成电路芯片外部的背面高速缓存器。背面缓存包括用于存储高速缓存地址标签和编码高速缓存状态位的目录RAM。第一总线将微处理器连接到高速缓存，第一总线包括背面总线缓存目录标签信号，其包括用于目录RAM中的高速缓存命中比较的地址位和用于确定目标RAM中的集合的状态编码的背面总线缓存目录状态位目录RAM。第二个总线将微处理器连接到主存储器。该目录包括用于将第一总线上的高速缓存目录标签与存储在目录中的标签进行比较并用于在存储在背面总线缓存目录中的目录标签与背面总线缓存目录标签不匹配的情况下断言Bmiss信号的装置信号。在缓存未命中的情况下，微处理器通过发出对第二总线的访问来响应Bmiss信号。

2. 发明授权

US4803622A Programmable I/O sequencer for use in an I/O processor 失效
标题翻译：用于I / O处理器的可编程I / O定序器
公开(公告)号：US4803622A
公开(公告)日：1989-02-07
申请号：US46633
申请日：1987-05-07
申请人： William L. Bain, Jr. , Robert C. Bedichek , George W. Cox , Gerhard Grassl , Craig B. Peterson , Justin R. Rattner , Gurbir Singh , Gurbir Singh , John L. Wipfli
发明人： William L. Bain, Jr. , Robert C. Bedichek , George W. Cox , Gerhard Grassl , Craig B. Peterson , Justin R. Rattner , Gurbir Singh , Gurbir Singh , John L. Wipfli
IPC分类号： G06F13/14 , G06F13/12 , G06F13/38 , G06F3/00
CPC分类号： G06F13/124
摘要： An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers. The PLA decodes an ACCESS instruction to start an operation by loading the first register set descriptor, and then decodes sequential SUPPLY instructions to the entry. Each SUPPLY instruction loads an empty register set descriptor field to be used when the current register set descriptor field is exhausted.
摘要翻译：一种用于在执行单元（EU-10），寄存器文件（14）和连接到总线（28）的设备之间提供数据路径的I / O总线定序器。可编程逻辑阵列（PLA-18）存储控制服务表（20）的程序。服务表包括分成字段的多个条目。解码后的其中一个字段指示PLA对总线音序器执行什么样的操作。连接到I / O请求线（30）和服务表（20）的线路选择（优先级）逻辑（22）确定PLA要使用的服务表条目。连接到I / O总线端口（26）和PLA（18）的总线接口在I / O总线端口（26）和寄存器文件（14）之间路由数据，其条目通过使用寄存器套。服务表字段包括用于存储寄存器组缓冲器的状态的寄存器集描述符。 PLA通过加载第一个寄存器集描述符对ACCESS指令进行解码以开始操作，然后将顺序的SUPPLY指令解码到该条目。每个SUPPLY指令加载当前寄存器集描述符字段耗尽时要使用的空寄存器集描述符字段。

3. 发明授权

US07836102B2 Method and system for enhancing software documentation and help systems 失效
公开(公告)号：US07836102B2
公开(公告)日：2010-11-16
申请号：US12345641
申请日：2008-12-29
申请人： Gurbir Singh
发明人： Gurbir Singh
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F8/73 , G06F9/453
摘要： A method and system for enhancing software documentation and help systems. In one embodiment, a virtual library for a selected combination of tools is created. The virtual library is then linked to the tools in the selected combination of tools. In another embodiment, a combination of tools for designing a complex software system is selected from one or more software releases. The one or more software releases comprises a plurality of available tools. The selected combination of tools comprises less than all of the plurality of available tools. Each of the plurality of available tools is associated with one or more documents. Access to only those one or more documents associated with tools in the selected combination of tools is provided.

4. 发明授权

US07262493B2 System and method for mounting electrical devices 有权
标题翻译：用于安装电气设备的系统和方法
公开(公告)号：US07262493B2
公开(公告)日：2007-08-28
申请号：US11030022
申请日：2005-01-06
申请人： Lee Sai Mun , Gurbir Singh , Seow Piang Joon
发明人： Lee Sai Mun , Gurbir Singh , Seow Piang Joon
IPC分类号： H01L23/02 , H01L23/48
CPC分类号： H01L27/14618 , H01L24/02 , H01L27/14683 , H01L31/0203 , H01L31/18 , H01L2924/01004 , H01L2924/01033 , H01L2924/01082
摘要： In one embodiment an electronic device, such as an optical sensor, is attached to a substrate upon which wire logouts and, if desired, other components are constructed. A frame, or cover, is attached to the substrate surrounding the attached device. An aperture in the cover allows wireless signals to pass in or out of the cover.
摘要翻译：在一个实施例中，诸如光学传感器的电子设备附接到基板上，在该基板上构造出线注销，并且如果需要，构建其它部件。框架或盖子附接到围绕附接装置的基板。盖子上的孔允许无线信号进入或离开盖子。

5. 发明授权

US06807592B2 Quad pumped bus architecture and protocol 失效
标题翻译：四泵浦总线架构和协议
公开(公告)号：US06807592B2
公开(公告)日：2004-10-19
申请号：US09925691
申请日：2001-08-10
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.
摘要翻译：双向多点处理器总线连接到多个总线代理。可以通过以多抽头信令模式操作总线来增加总线吞吐量，其中多个信息元素以驱动代理以总线时钟频率的倍数的速率被驱动到总线上。驱动代理还激活选通以识别信息元素的采样点。可以例如使用双泵浦信号模式来驱动请求的信息元素，其中在一个总线时钟周期期间驱动两个信息元素。数据线传输的数据元素例如可以使用四泵浦信号模式来驱动，其中四个数据元件在一个总线时钟周期内被驱动。可以以偏移或交错布置临时地激活多个选通信号，以减少选通信号的频率。可以通过仅使用选通信号的一种类型的边缘（例如，上升沿或下降沿）来提高采样对称性，以识别采样点。

6. 发明授权

US06804735B2 Response and data phases in a highly pipelined bus architecture 失效
标题翻译：高度流水线总线架构中的响应和数据阶段
公开(公告)号：US06804735B2
公开(公告)日：2004-10-12
申请号：US09784244
申请日：2001-02-14
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.
摘要翻译：可用于增强的高流水线总线架构中的总线代理。在一个实施例中，总线代理包括目标就绪接口，用于一组响应信号的一组响应接口和数据总线忙接口以及用于总线时钟信号的总线时钟接口。该实施例的总线代理还包括总线控制器逻辑以跟踪包括事务N-1和事务N的多个事务，总线控制器能够为事务N断言目标就绪信号，如果总线代理正在断言数据忙信号用于事务N-1，并取消对数据忙信号的否定。

7. 发明授权

US06311281B1 Apparatus and method for changing processor clock ratio settings 有权
标题翻译：改变处理器时钟比设置的装置和方法
公开(公告)号：US06311281B1
公开(公告)日：2001-10-30
申请号：US09261058
申请日：1999-03-02
申请人： Edwin J. Pole, II , John T. Orton , Cau L. Nguyen , Gurbir Singh , Xia Dai , Ravi Nagaraj
发明人： Edwin J. Pole, II , John T. Orton , Cau L. Nguyen , Gurbir Singh , Xia Dai , Ravi Nagaraj
IPC分类号： G06F104
CPC分类号： G06F1/08 , H03L7/06
摘要： A processor has an external pin that can be asserted to lock in new clock ratio information dynamically. A state machine of the processor defines a stop grant state that is utilized to halt the internal clocking signal of the processor. A storage location, such as a register, is utilized to load new clock frequency information into the clock generator circuit of the processor. De-asserting the external pin of the processor causes the processor to resume normal operations, but at the newly set clock frequency.
摘要翻译：一个处理器有一个外部引脚，可以被断言，以动态锁定新的时钟比率信息。处理器的状态机定义用于停止处理器的内部时钟信号的停止许可状态。诸如寄存器的存储位置被用于将新的时钟频率信息加载到处理器的时钟发生器电路中。取消断言处理器的外部引脚使处理器恢复正常操作，但处于新设定的时钟频率。

8. 发明授权

US5903738A Method and apparatus for performing bus transactions in a computer system 失效
标题翻译：用于在计算机系统中执行总线事务的方法和装置
公开(公告)号：US5903738A
公开(公告)日：1999-05-11
申请号：US715049
申请日：1996-09-17
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh
IPC分类号： G06F13/368 , G06F13/37 , G06F13/42 , G06F3/00
CPC分类号： G06F13/4213 , G06F13/368 , G06F13/37
摘要： A method and apparatus of performing bus transactions on the external bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：一种在计算机系统的外部总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

9. 发明授权

US07453516B2 Flexible camera lens barrel 有权
标题翻译：灵活的镜头镜筒
公开(公告)号：US07453516B2
公开(公告)日：2008-11-18
申请号：US10455283
申请日：2003-06-04
申请人： Shazli Husni , Gurbir Singh
发明人： Shazli Husni , Gurbir Singh
IPC分类号： H04N5/225
CPC分类号： H04N5/2254 , G02B7/00 , G02B13/001
摘要： A compact flexible camera lens barrel designed for use with mobile telephones. The lens barrel may be used separately or in conjunction with a camera housing. The lens barrel is designed for use with a variety of different components including cover glass, cover plastics, flanges, gaskets and the like. The components do not affect the original z-height of the lens barrel.
摘要翻译：设计用于移动电话的紧凑型柔性相机镜头镜筒。镜头筒可以单独使用或与相机外壳配合使用。透镜筒设计用于各种不同的部件，包括盖玻璃，盖塑料，法兰，垫圈等。这些组件不影响镜筒的原始z高度。

10. 发明授权

US06907487B2 Enhanced highly pipelined bus architecture 失效
标题翻译：增强高流水线总线架构
公开(公告)号：US06907487B2
公开(公告)日：2005-06-14
申请号：US09783852
申请日：2001-02-14
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F13/36 , G06F13/42 , G06F13/14
CPC分类号： G06F13/4217
摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.
摘要翻译：可用于增强的高流水线总线架构中的总线代理。在一个实施例中，总线代理包括用于以时钟频率驱动控制信号的控制接口，用于以两倍时钟频率驱动地址元件的地址总线接口和用于以四倍于时钟频率驱动数据元素的数据总线接口。地址总线接口为每个地址元件驱动基本中心的地址选通转换，并且数据总线接口为每个数据元件驱动基本中心的数据选通转换。

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