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1. 发明授权

US4803622A Programmable I/O sequencer for use in an I/O processor 失效
标题翻译：用于I / O处理器的可编程I / O定序器
公开(公告)号：US4803622A
公开(公告)日：1989-02-07
申请号：US46633
申请日：1987-05-07
申请人： William L. Bain, Jr. , Robert C. Bedichek , George W. Cox , Gerhard Grassl , Craig B. Peterson , Justin R. Rattner , Gurbir Singh , Gurbir Singh , John L. Wipfli
发明人： William L. Bain, Jr. , Robert C. Bedichek , George W. Cox , Gerhard Grassl , Craig B. Peterson , Justin R. Rattner , Gurbir Singh , Gurbir Singh , John L. Wipfli
IPC分类号： G06F13/14 , G06F13/12 , G06F13/38 , G06F3/00
CPC分类号： G06F13/124
摘要： An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers. The PLA decodes an ACCESS instruction to start an operation by loading the first register set descriptor, and then decodes sequential SUPPLY instructions to the entry. Each SUPPLY instruction loads an empty register set descriptor field to be used when the current register set descriptor field is exhausted.
摘要翻译：一种用于在执行单元（EU-10），寄存器文件（14）和连接到总线（28）的设备之间提供数据路径的I / O总线定序器。可编程逻辑阵列（PLA-18）存储控制服务表（20）的程序。服务表包括分成字段的多个条目。解码后的其中一个字段指示PLA对总线音序器执行什么样的操作。连接到I / O请求线（30）和服务表（20）的线路选择（优先级）逻辑（22）确定PLA要使用的服务表条目。连接到I / O总线端口（26）和PLA（18）的总线接口在I / O总线端口（26）和寄存器文件（14）之间路由数据，其条目通过使用寄存器套。服务表字段包括用于存储寄存器组缓冲器的状态的寄存器集描述符。 PLA通过加载第一个寄存器集描述符对ACCESS指令进行解码以开始操作，然后将顺序的SUPPLY指令解码到该条目。每个SUPPLY指令加载当前寄存器集描述符字段耗尽时要使用的空寄存器集描述符字段。

2. 发明授权

US4517672A Method and arrangement for an operational check of a programmable logic array 失效
标题翻译：用于可编程逻辑阵列的操作检查的方法和装置
公开(公告)号：US4517672A
公开(公告)日：1985-05-14
申请号：US401229
申请日：1982-07-23
申请人： Hans-Joerg Pfleiderer , Gerhard Grassl
发明人： Hans-Joerg Pfleiderer , Gerhard Grassl
IPC分类号： G06F11/22 , G01R31/3185 , H03K19/177 , G06F11/00
CPC分类号： G01R31/318516
摘要： A function check of a programmable logic array is performed in which input lines, product term lines and ground lines are combined into an AND plane and output lines, product term lines and ground lines are combined into an OR plane. The aim is a simple method of function check which permits any potentially-existing fault to be detected. The check is achieved by generating, with a test data generator, bit patterns and applying the same to the input lines, and, through the use of a shift register, successively sensitizing the product term lines either individually or in groups, i.e. disconnecting the same from ground potential. The bit patterns occurring at the output lines are supplied to a test data evaluator. The area of use is in logic circuitry of data processing technology.
摘要翻译：执行可编程逻辑阵列的功能检查，其中将输入线，乘积项线和接地线组合成AND平面，并将输出线，乘积项线和接地线组合成OR平面。目的是一种简单的功能检查方法，可以检测任何潜在的故障。通过使用测试数据发生器生成位模式并将其应用于输入线路来实现该检查，并且通过使用移位寄存器，对产品项目线路单独或分组地依次敏感化，即断开相同的从地电位。在输出线上发生的位模式被提供给测试数据评估器。使用的领域是数据处理技术的逻辑电路。

3. 发明授权

US4250568A Capacitor semiconductor storage circuit 失效
标题翻译：电容半导体存储电路
公开(公告)号：US4250568A
公开(公告)日：1981-02-10
申请号：US98123
申请日：1979-11-28
申请人： Gerhard Grassl
发明人： Gerhard Grassl
IPC分类号： H01L29/78 , G11C5/06 , G11C11/24 , H01L21/8246 , H01L27/10 , H01L27/108 , H01L27/112
CPC分类号： H01L27/108 , G11C11/24 , G11C5/063
摘要： A semiconductor storage circuit has a plurality of storage elements which are provided with storage capacitors and which are grouped in rows and columns and integrated on a doped semiconductor body. The storage elements which form a row are provided with a common first drive line and the storage elements which form a column are provided with a second common drive line. The first drive lines are formed from strip-like electrically conductive layers which are separated by an insulating layer from the surface of the semiconductor body and the second drive lines consist of buried lines which extend within the semiconductor body and are oppositely doped with respect to the body. The insulating layer is designed to be thinner within the intersection zones of the drive lines so that in these zones insulating layer capacitors are formed which possess outer electrodes composed of parts of the first drive lines and which represent storage capacitors of the storage elements. The widths of the buried lines which represent the second drive lines are designed to be less than the dimensions, oriented transversely to these strips, of the outer electrodes, and between the buried lines which represent the second drive lines further buried lines are arranged which can be connected by way of terminals to a voltage source.
摘要翻译：半导体存储电路具有多个存储元件，其具有存储电容器，并且被分组成行和列，并且集成在掺杂的半导体本体上。形成行的存储元件设置有公共第一驱动线，并且形成列的存储元件设置有第二公共驱动线。第一驱动线由条形导电层形成，该导电层由绝缘层与半导体本体的表面隔开，第二驱动线由在半导体本体内延伸并且相对于身体。绝缘层被设计为在驱动线的交叉区域内更薄，使得在这些区域中形成绝缘层电容器，其具有由第一驱动线的部分组成并且表示存储元件的存储电容器的外部电极。表示第二驱动线的掩埋线的宽度被设计为小于外部电极横向于这些条的尺寸，并且在表示第二驱动线的掩埋线之间布置另外的掩埋线，其可以通过端子连接到电压源。

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