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1. 发明申请

US20110161780A1 METHOD AND SYSTEM FOR PROVIDING AN IMPROVED STORE-IN CACHE 有权
标题翻译：提供改进存储缓存的方法和系统
公开(公告)号：US20110161780A1
公开(公告)日：2011-06-30
申请号：US13041248
申请日：2011-03-04
申请人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： G06F12/0802 , G06F11/1064 , G06F11/1666
摘要： A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.
摘要翻译：硬化的存储缓存系统包括具有存储有校验位的第一行的行的存储高速缓存，其中校验位包括字节奇偶校验位，以及保存最近存储的副本的辅助存储高速缓存（ASOC）到存储缓存中的行。 ASOC包括比存储缓存更少的行，ASOC的每一行都具有与检查位一起存储的第一行。

2. 发明授权

US08826095B2 Method and system for providing an improved store-in cache 有权
标题翻译：用于提供改进的存储缓存的方法和系统
公开(公告)号：US08826095B2
公开(公告)日：2014-09-02
申请号：US13041248
申请日：2011-03-04
申请人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： H03M13/00
CPC分类号： G06F12/0802 , G06F11/1064 , G06F11/1666
摘要： A hardened store-in cache system includes a store-in cache having lines of a first linesize stored with checkbits, wherein the checkbits include byte-parity bits, and an ancillary store-only cache (ASOC) that holds a copy of most recently stored-to lines of the store-in cache. The ASOC includes fewer lines than the store-in cache, each line of the ASOC having the first linesize stored with the checkbits.
摘要翻译：硬化的存储缓存系统包括具有存储有校验位的第一行的行的存储高速缓存，其中校验位包括字节奇偶校验位，以及保存最近存储的副本的辅助存储高速缓存（ASOC）到存储缓存中的行。 ASOC包括比存储缓存更少的行，ASOC的每一行都具有与检查位一起存储的第一行。

3. 发明申请

US20080222358A1 METHOD AND SYSTEM FOR PROVIDING AN IMPROVED STORE-IN CACHE 有权
标题翻译：提供改进存储缓存的方法和系统
公开(公告)号：US20080222358A1
公开(公告)日：2008-09-11
申请号：US11683285
申请日：2007-03-07
申请人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F11/1064 , G06F11/1666
摘要： A system and method of providing a cache system having a store-in policy and affording the advantages of store-in cache operation, while simultaneously providing protection against soft-errors in locally modified data, which would normally preclude the use of a store-in cache when reliability is paramount. The improved store-in cache mechanism includes a store-in L1 cache, at least one higher-level storage hierarchy; an ancillary store-only cache (ASOC) that holds most recently stored-to lines of the store-in L1 cache, and a cache controller that controls storing of data to the ancillary store-only cache (ASOC) and recovering of data from the ancillary store-only cache (ASOC) such that the data from the ancillary store-only cache (ASOC) is used only if parity errors are encountered in the store-in L1 cache.
摘要翻译：提供具有存储策略并提供存储高速缓存操作的优点的缓存系统的系统和方法，同时提供对本地修改的数据中的软错误的保护，这通常会阻止使用存储缓存当可靠性至关重要时。改进的存储高速缓存机制包括存储L1高速缓存，至少一个更高级别的存储层级; 保存最近存储在L1高速缓存中的行的辅助存储专用缓存（ASOC）以及控制将数据存储到辅助存储高速缓存（ASOC）并从辅助存储高速缓存（ASOC），使得只有在存储的L1高速缓存中遇到奇偶校验错误时才使用来自辅助存储高速缓存（ASOC）的数据。

4. 发明授权

US07941728B2 Method and system for providing an improved store-in cache 有权
标题翻译：用于提供改进的存储缓存的方法和系统
公开(公告)号：US07941728B2
公开(公告)日：2011-05-10
申请号：US11683285
申请日：2007-03-07
申请人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip George Emma , Wing K. Luk , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： H03M13/00
CPC分类号： G06F12/0802 , G06F11/1064 , G06F11/1666
摘要： A system and method of providing a cache system having a store-in policy and affording the advantages of store-in cache operation, while simultaneously providing protection against soft-errors in locally modified data, which would normally preclude the use of a store-in cache when reliability is paramount. The improved store-in cache mechanism includes a store-in L1 cache, at least one higher-level storage hierarchy; an ancillary store-only cache (ASOC) that holds most recently stored-to lines of the store-in L1 cache, and a cache controller that controls storing of data to the ancillary store-only cache (ASOC) and recovering of data from the ancillary store-only cache (ASOC) such that the data from the ancillary store-only cache (ASOC) is used only if parity errors are encountered in the store-in L1 cache.
摘要翻译：提供具有存储策略并提供存储高速缓存操作的优点的缓存系统的系统和方法，同时提供对本地修改的数据中的软错误的保护，这通常会阻止使用存储缓存当可靠性至关重要时。改进的存储高速缓存机制包括存储L1高速缓存，至少一个更高级别的存储层级; 保存最近存储在L1高速缓存中的行的辅助存储专用缓存（ASOC）以及控制将数据存储到辅助存储高速缓存（ASOC）并从辅助存储高速缓存（ASOC），使得只有在存储的L1高速缓存中遇到奇偶校验错误时才使用来自辅助存储高速缓存（ASOC）的数据。

5. 发明申请

US20080010555A1 Method and Apparatus for Measuring the Cost of a Pipeline Event and for Displaying Images Which Permit the Visualization orf Said Cost 审中-公开
标题翻译：用于测量管道事件的成本和显示允许可视化或所述成本的图像的方法和装置
公开(公告)号：US20080010555A1
公开(公告)日：2008-01-10
申请号：US11424696
申请日：2006-06-16
申请人： Phillip Emma , Alian Hartstein , Daniel N. Lynch , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Phillip Emma , Alian Hartstein , Daniel N. Lynch , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： G06F11/00
CPC分类号： G06F11/3423 , G06F11/3476 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A hardware monitor is used to monitor the sequence of instructions executed during a miss cluster. The monitor groups each cache miss into a miss cluster, and the miss penalty associated with each cluster is determined by identifying a set of instructions that were executed during the miss cluster. The finite cache running time is then calculated for the set of instructions that occurred during the miss cluster. Additionally, an infinite cache running time is determined for the same set of instructions that occurred during the miss cluster, where the infinite cache running time is the time needed to execute this set of instructions in the absence of any miss. The cost of the miss cluster is then calculated by measuring the difference between the finite cache running time and the infinite cache running time.
摘要翻译：硬件监视器用于监视在小组群集期间执行的指令序列。监视器将每个高速缓存未命中组合成一个未命中集群，并且通过识别一组在缺少集群期间执行的指令来确定与每个集群相关联的丢失代价。然后针对在缺少集群期间发生的指令集计算有限缓存运行时间。另外，对于在缺少集群期间发生的相同指令集，确定无限缓存运行时间，其中无限高速缓存运行时间是在没有任何缺失的情况下执行该组指令所需的时间。然后，通过测量有限缓存运行时间和无限缓存运行时间之间的差异来计算小数簇的成本。

6. 发明授权

US08521999B2 Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history 有权
标题翻译：执行touchBHT指令，预先获取信息到具有历史记录的分支预测机制
公开(公告)号：US08521999B2
公开(公告)日：2013-08-27
申请号：US12721933
申请日：2010-03-11
申请人： Philip G. Emma , Allan M. Hartstein , Brian R. Prasky , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Allan M. Hartstein , Brian R. Prasky , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30058 , G06F9/30145 , G06F9/3846 , G06F9/3848
摘要： A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken.
摘要翻译：一种方法，包括接收分支指令，解码分支地址和分支指令，执行与分支地址相关联的分支动作，确定是否采用与分支动作相关联的分支，以及保存分支指令的标识符和指示符响应于确定与分支动作相关联的分支被采取，分支动作被采取在预取历史表中。

7. 发明授权

US07493480B2 Method and apparatus for prefetching branch history information 失效
标题翻译：用于预取分支历史信息的方法和装置
公开(公告)号：US07493480B2
公开(公告)日：2009-02-17
申请号：US10197714
申请日：2002-07-18
申请人： Philip G. Emma , Klaus J. Getzlaff , Allan M. Hartstein , Thomas Pflueger , Thomas R. Puzak , Eric Mark Schwarz , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Klaus J. Getzlaff , Allan M. Hartstein , Thomas Pflueger , Thomas R. Puzak , Eric Mark Schwarz , Vijayalakshmi Srinivasan
IPC分类号： G06F9/00
CPC分类号： G06F9/3806
摘要： A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor uses them in the branch prediction process and at the same time prefetch cache misses into the instruction cache. The mechanism prefetches entries from the very large L2 BHT into the very fast L1 BHT before the processor uses them in the branch prediction process. A TLBHT is successful because it can prefetch branch entries into the L1 BHT sufficiently ahead of the time the entry is needed. This feature of the TLBHT is also used to prefetch instructions into the cache ahead of their use. In fact, the timeliness of the prefetches produced by the TLBHT can be used to remove most of the cycle time penalty incurred by cache misses.
摘要翻译：通过提供一种将超大型第二级分支历史表（L2 BHT）中的条目预取到活动（非常快）的第一级分支历史表（L1 BHT）中的条目之前，两级分支历史表（TLBHT）被大大改善处理器在分支预测过程中使用它们，并且同时将高速缓存未命中预取到指令高速缓存中。在处理器在分支预测过程中使用它们之前，该机制将从非常大的L2 BHT中将条目预取到非常快的L1 BHT中。 TLBHT是成功的，因为它可以在需要输入的时间之前将分支条目预取到L1 BHT中。 TLBHT的这个功能也用于在使用之前将指令预取到高速缓存中。实际上，由TLBHT产生的预取的及时性可以用来消除高速缓存未命中引起的大部分周期时间损失。

8. 发明申请

US20110225401A1 PREFETCHING BRANCH PREDICTION MECHANISMS 有权
标题翻译：预分支预测机制
公开(公告)号：US20110225401A1
公开(公告)日：2011-09-15
申请号：US12721933
申请日：2010-03-11
申请人： Philip G. Emma , Allan M. Hartstein , Brian R. Prasky , Thomas R. Puzak , Vijayalakshmi Srinivasan
发明人： Philip G. Emma , Allan M. Hartstein , Brian R. Prasky , Thomas R. Puzak , Vijayalakshmi Srinivasan
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30058 , G06F9/30145 , G06F9/3846 , G06F9/3848
摘要： A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken.
摘要翻译：一种方法，包括接收分支指令，解码分支地址和分支指令，执行与分支地址相关联的分支动作，确定是否采用与分支动作相关联的分支，以及保存分支指令的标识符和指示符响应于确定与分支动作相关联的分支被采取，分支动作被采取在预取历史表中。

9. 发明授权

US06560693B1 Branch history guided instruction/data prefetching 失效
标题翻译：分支历史指导/数据预取
公开(公告)号：US06560693B1
公开(公告)日：2003-05-06
申请号：US09459739
申请日：1999-12-10
申请人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden , Vijayalakshmi Srinivasan
发明人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden , Vijayalakshmi Srinivasan
IPC分类号： G06F1500
CPC分类号： G06F9/383 , G06F9/30047 , G06F9/3455 , G06F9/3836 , G06F9/3844
摘要： A mechanism is described that prefetches instructions and data into the cache using a branch instruction as a prefetch trigger. The prefetch is initiated if the predicted execution path after the branch instruction matches the previously seen execution path. This match of the execution paths is determined using a branch history queue that records the branch outcomes (taken/not taken) of the branches in the program. For each branch in this queue, a branch history mask records the outcomes of the next N branches and serves as an encoding of the execution path following the branch instruction. The branch instruction along with the mask is associated with a prefetch address (instruction or data address) and is used for triggering prefetches in the future when the branch is executed again. A mechanism is also described to improve the timeliness of a prefetch by suitably adjusting the value of N after observing the usefulness of the prefetched instructions or data.
摘要翻译：描述了使用分支指令作为预取触发器将指令和数据预取到高速缓存中的机制。如果分支指令之后的预测执行路径与先前查看的执行路径匹配，则启动预取。使用分支历史队列确定执行路径的这种匹配，该分支历史队列记录节目中分支的分支结果（已取/未采用）。对于该队列中的每个分支，分支历史掩码记录下一个N个分支的结果，并且作为分支指令之后的执行路径的编码。分支指令与掩码一起与预取地址（指令或数据地址）相关联，并且在再次执行分支时用于触发预取。还描述了一种机制，以通过在观察到预取指令或数据的有用性之后适当地调整N的值来提高预取的及时性。

10. 发明授权

US09176876B2 Selective cache-to-cache lateral castouts 有权
公开(公告)号：US09176876B2
公开(公告)日：2015-11-03
申请号：US13445646
申请日：2012-04-12
申请人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

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