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1. 发明授权

US06560693B1 Branch history guided instruction/data prefetching 失效
标题翻译：分支历史指导/数据预取
公开(公告)号：US06560693B1
公开(公告)日：2003-05-06
申请号：US09459739
申请日：1999-12-10
申请人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden , Vijayalakshmi Srinivasan
发明人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden , Vijayalakshmi Srinivasan
IPC分类号： G06F1500
CPC分类号： G06F9/383 , G06F9/30047 , G06F9/3455 , G06F9/3836 , G06F9/3844
摘要： A mechanism is described that prefetches instructions and data into the cache using a branch instruction as a prefetch trigger. The prefetch is initiated if the predicted execution path after the branch instruction matches the previously seen execution path. This match of the execution paths is determined using a branch history queue that records the branch outcomes (taken/not taken) of the branches in the program. For each branch in this queue, a branch history mask records the outcomes of the next N branches and serves as an encoding of the execution path following the branch instruction. The branch instruction along with the mask is associated with a prefetch address (instruction or data address) and is used for triggering prefetches in the future when the branch is executed again. A mechanism is also described to improve the timeliness of a prefetch by suitably adjusting the value of N after observing the usefulness of the prefetched instructions or data.
摘要翻译：描述了使用分支指令作为预取触发器将指令和数据预取到高速缓存中的机制。如果分支指令之后的预测执行路径与先前查看的执行路径匹配，则启动预取。使用分支历史队列确定执行路径的这种匹配，该分支历史队列记录节目中分支的分支结果（已取/未采用）。对于该队列中的每个分支，分支历史掩码记录下一个N个分支的结果，并且作为分支指令之后的执行路径的编码。分支指令与掩码一起与预取地址（指令或数据地址）相关联，并且在再次执行分支时用于触发预取。还描述了一种机制，以通过在观察到预取指令或数据的有用性之后适当地调整N的值来提高预取的及时性。

2. 发明授权

US07441110B1 Prefetching using future branch path information derived from branch prediction 失效
标题翻译：使用从分支预测得到的未来分支路径信息进行预取
公开(公告)号：US07441110B1
公开(公告)日：2008-10-21
申请号：US09458883
申请日：1999-12-10
申请人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden
发明人： Thomas R. Puzak , Allan M. Hartstein , Mark Charney , Daniel A. Prener , Peter H. Oden
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/4442 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F9/3844
摘要： A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while instructions that are predicted as not useful are discarded. The prediction regarding the usefulness of a prefetching instructions is performed utilizing a branch prediction mask contained in the branch history mechanism. This mask is compared to information contained in the prefetching instruction that records the branch path between the prefetching instruction and actual use of the data. Both instructions and data can be prefetched using this mechanism.
摘要翻译：描述了一种机制，其预测在指令的解码周期期间预取指令的有用性。被预测为有用的预取指令（预取有用数据）被发送到处理器的执行单元用于执行，而被预测为无用的指令被丢弃。使用包含在分支历史机制中的分支预测掩模来执行关于预取指令的有用性的预测。将该掩码与包含在预取指令中的信息进行比较，该预取指令记录预取指令和数据的实际使用之间的分支路径。可以使用这种机制来预取指令和数据。

3. 发明授权

US06311253B1 Methods for caching cache tags 失效
标题翻译：高速缓存标记缓存方法
公开(公告)号：US06311253B1
公开(公告)日：2001-10-30
申请号：US09336953
申请日：1999-06-21
申请人： Albert Chang , Mark Charney , Robert K. Montoye , Thomas R. Puzak
发明人： Albert Chang , Mark Charney , Robert K. Montoye , Thomas R. Puzak
IPC分类号： G06F1208
CPC分类号： G06F12/0897 , G06F12/0864
摘要： A method for storing information in a computer memory system includes maintaining an Mth level storage system including an Mth level data store for storing data, an Mth level full directory for storing a set of tags corresponding to the data, and an Mth level partial directory for storing a subset of the tags. The partial directory is accessible faster than the full directory. Upon an M-1 level miss corresponding to a request for data, a congruence class corresponding to the request is fetched from the partial directory when it is present therein; otherwise, it is fetched from the full directory. The requested data is retrieved from the data store when it is present in the congruence class; otherwise, it is retrieved from a next level of the memory system. The tags in the partial directory may be full tags, partial tags, or a combination thereof.
摘要翻译：一种用于在计算机存储器系统中存储信息的方法包括维护包括用于存储数据的第M级数据存储器的第M级存储系统，用于存储对应于数据的一组标签的第M级完整目录，以及用于存储标签的子集。部分目录可访问速度快于完整目录。在与数据请求相对应的M-1级丢失时，当存在对应于该请求的等同类时，从部分目录中取出; 否则，它将从完整目录中获取。当数据存储在同余类中时，从数据存储中检索所请求的数据; 否则，它从存储器系统的下一级检索。部分目录中的标签可以是完整标签，部分标签或其组合。

4. 发明授权

US09600285B2 Packed data operation mask concatenation processors, methods, systems and instructions 有权
公开(公告)号：US09600285B2
公开(公告)日：2017-03-21
申请号：US13977239
申请日：2011-12-22
申请人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
发明人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
IPC分类号： G06F15/00 , G06F15/76 , G06F9/30 , G06F13/14
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3013 , G06F13/14
摘要： A method of an aspect includes receiving a packed data operation mask concatenation instruction. The packed data operation mask concatenation instruction indicates a first source having a first packed data operation mask, indicates a second source having a second packed data operation mask, and indicates a destination. A result is stored in the destination in response to the packed data operation mask concatenation instruction. The result includes the first packed data operation mask concatenated with the second packed data operation mask. Other methods, apparatus, systems, and instructions are disclosed.

5. 发明申请

US20160188341A1 APPARATUS AND METHOD FOR FUSED ADD-ADD INSTRUCTIONS 审中-公开
标题翻译：用于加热添加指令的装置和方法
公开(公告)号：US20160188341A1
公开(公告)日：2016-06-30
申请号：US14583050
申请日：2014-12-24
申请人： Elmoustapha OULD-AHMED-VALL , Robert Valentine , Jesus Corbal , Mark Charney , Roger Espasa , Guillem Sole , Manel Fernandez , Brian J. Hickmann
发明人： Elmoustapha OULD-AHMED-VALL , Robert Valentine , Jesus Corbal , Mark Charney , Roger Espasa , Guillem Sole , Manel Fernandez , Brian J. Hickmann
IPC分类号： G06F9/30
CPC分类号： G06F9/30196 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30167
摘要： In one embodiment of the invention, a processor including a storage location configured to store a set of source packed-data operands, each of the operands having a plurality of packed-data elements that are positive or negative according to an immediate bit value within one of the operands. The processor also including: a decoder to decode an instruction requiring an input of a plurality of source operands, and an execution unit to receive the decoded instructions and to generate a result that is a sum of the source operands. In one embodiment, the result is stored back into one of the source operands or the result is stored into an operand that is independent of the source operands.
摘要翻译：在本发明的一个实施例中，一种包括存储位置的处理器，被配置为存储一组源压缩数据操作数，每个操作数具有多个压缩数据元素，这些数据元素根据一个中的立即位值为正或负的操作数。处理器还包括：解码器，用于解码需要多个源操作数的输入的指令，以及执行单元，用于接收解码的指令并产生作为源操作数之和的结果。在一个实施例中，将结果存储回源操作数之一，或将结果存储到独立于源操作数的操作数中。

6. 发明申请

US20190102184A1 APPARATUS AND METHOD FOR SHIFTING QUADWORDS AND EXTRACTING PACKED WORDS 审中-公开
公开(公告)号：US20190102184A1
公开(公告)日：2019-04-04
申请号：US15721466
申请日：2017-09-29
申请人： Venkateswara Madduri , Elmoustapha Ould-Ahmed-Vall , Jesus Corbal , Mark Charney , Robert Valentine , Binwei Yang
发明人： Venkateswara Madduri , Elmoustapha Ould-Ahmed-Vall , Jesus Corbal , Mark Charney , Robert Valentine , Binwei Yang
IPC分类号： G06F9/30
摘要： An apparatus and method for performing right-shifting operations on packed quadword data. For example, one embodiment of a processor comprises: a decoder to decode a right-shift instruction to generate a decoded right-shift instruction; a first source register to store a plurality of packed quadwords data elements; execution circuitry to execute the decoded right-shift instruction, the execution circuitry comprising shift circuitry to right-shift at least first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, to generate first and second right-shifted quadwords; the execution circuitry to cause selection of 16 most significant bits of the first and second right-shifted quadwords to be written to 16 least significant bit regions of first and second quadword data element locations, respectively, of a destination register; and the destination register to store the specified set of the 16 most significant bits of the first and second right-shifted quadwords.

7. 发明申请

US20050091121A1 Method and apparatus for efficient ordered stores over an interconnection network 有权
标题翻译：通过互连网络实现有效存储的方法和装置
公开(公告)号：US20050091121A1
公开(公告)日：2005-04-28
申请号：US10691176
申请日：2003-10-22
申请人： Mark Charney , Ravi Rajwar , Pritpal Ahuja , Matthew Mattina
发明人： Mark Charney , Ravi Rajwar , Pritpal Ahuja , Matthew Mattina
IPC分类号： G06F12/08 , G06F17/60
CPC分类号： G06F12/0813 , G06Q30/0601
摘要： A physically distributed cache memory system includes an interconnection network, first level cache memory slices, and second level cache memory slices. The first level cache memory slices are coupled to the interconnection network to generate tagged ordered store requests. Each tagged ordered store requests has a tag including requester identification and a store sequence token. The second level cache memory slices are coupled to the interconnection network to execute ordered store requests in-order across the physically distributed cache memory system in response to each tag of the tagged ordered store requests.
摘要翻译：物理分布式高速缓冲存储器系统包括互连网络，第一级高速缓存存储器片和第二级高速缓存存储器片。第一级缓存存储器片耦合到互连网络以生成标记的有序存储请求。每个标记的有序存储请求都具有包括请求者标识和存储序列令牌的标签。第二级高速缓存存储器片耦合到互连网络，以响应于标记的有序存储请求的每个标签跨物理分布式高速缓冲存储器系统按顺序执行有序存储请求。

8. 发明授权

US09244687B2 Packed data operation mask comparison processors, methods, systems, and instructions 有权
标题翻译：打包数据操作掩码比较处理器，方法，系统和指令
公开(公告)号：US09244687B2
公开(公告)日：2016-01-26
申请号：US13977153
申请日：2011-12-29
申请人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
发明人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/30189 , G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/30145
摘要： Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.
摘要翻译：接收指示具有第一打包数据操作屏蔽位的第一打包数据操作掩码的打包数据操作掩码比较指令和具有第二打包数据操作掩码位的第二打包数据操作掩码。第一掩码的每个打包数据操作屏蔽位对应于相应位置的第二掩码的打包数据操作屏蔽位。将第一个掩码的每个打包数据操作屏蔽位的按位AND和第二个掩码的每个对应的打包数据操作掩码位的第一个值修改为第一个值为零。否则将第一个标志修改为第二个值。如果第二掩码的每个对应的打包数据操作屏蔽位的按位NOT的第一掩码的每个打包数据操作屏蔽位的按位AND为零，则将第二标志修改为第三值。否则将第二个标志修改为第四个值。

9. 发明申请

US20140289503A1 PACKED DATA OPERATION MASK COMPARISON PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
标题翻译：包装数据操作掩码比较处理器，方法，系统和指令
公开(公告)号：US20140289503A1
公开(公告)日：2014-09-25
申请号：US13977153
申请日：2011-12-29
申请人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
发明人： Bret L. Toll , Robert Valentine , Jesus Corbal San Adrian , Elmoustapha Ould-Ahmed-Vall , Mark Charney
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/30145
摘要： Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.
摘要翻译：接收指示具有第一打包数据操作屏蔽位的第一打包数据操作掩码的打包数据操作掩码比较指令和具有第二打包数据操作掩码位的第二打包数据操作掩码。第一掩码的每个打包数据操作屏蔽位对应于相应位置的第二掩码的打包数据操作屏蔽位。将第一个掩码的每个打包数据操作屏蔽位的按位AND和第二个掩码的每个对应的打包数据操作掩码位的第一个值修改为第一个值为零。否则将第一个标志修改为第二个值。如果第二掩码的每个对应的打包数据操作屏蔽位的按位NOT的第一掩码的每个打包数据操作屏蔽位的按位AND为零，则将第二标志修改为第三值。否则将第二个标志修改为第四个值。

10. 发明申请

US20140149724A1 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 审中-公开
标题翻译：向导友好指示格式及其执行
公开(公告)号：US20140149724A1
公开(公告)日：2014-05-29
申请号：US14170397
申请日：2014-01-31
申请人： Robert C. Valentine , Jesus Corbal San Adrian , Roger Espasa Sans , Robert D. Cavin , Bret L. Toll , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Edward Thomas Grochowski , Jonathan Cannon Hall , Dennis R. Bradford , Elmoustapha Ould-Ahmed-Vall , James C. Abel , Mark Charney , Seth Abraham , Suleyman Sair , Andrew Thomas Forsyth , Lisa Wu , Charles Yount
发明人： Robert C. Valentine , Jesus Corbal San Adrian , Roger Espasa Sans , Robert D. Cavin , Bret L. Toll , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Edward Thomas Grochowski , Jonathan Cannon Hall , Dennis R. Bradford , Elmoustapha Ould-Ahmed-Vall , James C. Abel , Mark Charney , Seth Abraham , Suleyman Sair , Andrew Thomas Forsyth , Lisa Wu , Charles Yount
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30149 , G06F9/30185 , G06F9/30192 , G06F9/34
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
摘要翻译：一种向量友好的指令格式及其执行。根据本发明的一个实施例，处理器被配置为执行指令集。指令集包括向量友好指令格式。向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作，基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段，在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。

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