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1. 发明授权

US5633877A Programmable built-in self test method and controller for arrays 失效
标题翻译：可编程内置自检方法和阵列控制器
公开(公告)号：US5633877A
公开(公告)日：1997-05-27
申请号：US450585
申请日：1995-05-31
申请人： Philip G. Shephard, III , William V. Huott , Paul R. Turgeon , Robert W. Berry, Jr. , Gulsun Yasar , Frederick J. Cox , Pradip Patel , Joseph B. Hanley, III
发明人： Philip G. Shephard, III , William V. Huott , Paul R. Turgeon , Robert W. Berry, Jr. , Gulsun Yasar , Frederick J. Cox , Pradip Patel , Joseph B. Hanley, III
IPC分类号： G06F11/22 , G06F11/267 , G06F11/273 , G11C29/00 , G11C29/10 , G11C29/16 , G11C29/32 , G06F11/00
CPC分类号： G11C29/789 , G01R31/318385 , G06F11/22 , G06F11/2236 , G06F11/2294 , G11C29/16 , G11C29/10 , G11C29/32
摘要： An array built-in self test system has a scannable memory elements and a controller which, in combination, allow self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy.
摘要翻译：阵列内置的自检系统具有可扫描的存储器元件和控制器，其组合地允许在不对测试逻辑进行硬件改变的情况下修改自检功能（例如测试模式，读/写访问和测试序列）。测试顺序由逻辑测试向量控制，可以改变，使得开发复杂测试序列的任务比较容易。

2. 发明授权

US5375091A Method and apparatus for memory dynamic burn-in and test 失效
标题翻译：用于记忆动态老化和测试的方法和装置
公开(公告)号：US5375091A
公开(公告)日：1994-12-20
申请号：US163803
申请日：1993-12-08
申请人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
发明人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
IPC分类号： G11C29/10 , G11C29/50 , G11C13/00
CPC分类号： G11C29/10 , G11C29/50
摘要： A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register. A plurality of independent circulating loops may be created in the data input register or in combination with a number of dummy register bits.
摘要翻译：嵌入在集成处理器芯片中的存储器通过重复地将测试图案写入存储器的数据位置而被动态地受到压力测试，其中高百分比的存储器单元被顺序地写有补充数据，以便在存储器上产生高应力设备。作为存储器的地址位置的数量和存储器数据字的数据位的数量的函数产生测试图案。每次存储器寻址时，测试模式都会旋转。测试图案优选地具有连续的数字组，连续组中的位数是作为存储器字中的地址位置数和数据位数的函数。存储器数据输入寄存器被配置为循环回路，并添加额外的虚拟位以提供比数据输入寄存器更长的再循环回路。可以在数据输入寄存器中或与多个虚拟寄存器位组合地产生多个独立的循环回路。

3. 发明申请

US20090183130A1 System and Method for Improved Hierarchical Analysis of Electronic Circuits 有权
标题翻译：改进电子电路分层分析的系统与方法
公开(公告)号：US20090183130A1
公开(公告)日：2009-07-16
申请号：US11972923
申请日：2008-01-11
申请人： Philip G. Shephard, III , Ravichander Ledalla , Vasant Rao , Jeffrey P. Soreff
发明人： Philip G. Shephard, III , Ravichander Ledalla , Vasant Rao , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.
摘要翻译：一种用于电子电路的层次分析的方法包括选择通用设计模型（GDM）的多个抽象层中的第一个抽象层。 GDM包括在多个抽象级别的电子电路的第一设计描述和被组织成子块的多个焦点。该方法选择多个焦点的第一焦点以选择第一子块。该方法识别所选择的第一子块中不完整的电子电路。该方法产生第一子块的第二设计描述以排除所识别的不完整电子电路，其中第二设计描述适用于电子设计分析（EDA）。该方法存储生成的第二设计描述供后续使用。随后的迭代因此包括在先前迭代中不完整的电路的所有组件。

4. 发明授权

US07870515B2 System and method for improved hierarchical analysis of electronic circuits 有权
标题翻译：改进电子电路层次分析的系统和方法
公开(公告)号：US07870515B2
公开(公告)日：2011-01-11
申请号：US11972923
申请日：2008-01-11
申请人： Philip G. Shephard, III , Ravichander Ledalla , Vasant Rao , Jeffrey P. Soreff
发明人： Philip G. Shephard, III , Ravichander Ledalla , Vasant Rao , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.
摘要翻译：一种用于电子电路的层次分析的方法包括选择通用设计模型（GDM）的多个抽象层中的第一个抽象层。 GDM包括在多个抽象级别的电子电路的第一设计描述和被组织成子块的多个焦点。该方法选择多个焦点的第一焦点以选择第一子块。该方法识别所选择的第一子块中不完整的电子电路。该方法产生第一子块的第二设计描述以排除所识别的不完整电子电路，其中第二设计描述适用于电子设计分析（EDA）。该方法存储生成的第二设计描述供后续使用。随后的迭代因此包括在先前迭代中不完整的电路的所有组件。

5. 发明授权

US07073106B2 Test method for guaranteeing full stuck-at-fault coverage of a memory array 失效
标题翻译：用于确保存储器阵列的完全卡在故障覆盖的测试方法
公开(公告)号：US07073106B2
公开(公告)日：2006-07-04
申请号：US10392665
申请日：2003-03-19
申请人： Jose A. Paredes , Philip G. Shephard, III , Timothy M. Skergan , Neil R. Vanderschaaf
发明人： Jose A. Paredes , Philip G. Shephard, III , Timothy M. Skergan , Neil R. Vanderschaaf
IPC分类号： G11C29/00
CPC分类号： G11C29/024 , G11C15/00 , G11C29/02
摘要： A method, computer program product and system for testing stuck-at-faults. A first register may be loaded with a first value where the first value may be written into each entry in a memory array. A second register may be loaded with a second value. A third register may be loaded with either the second value or a third value. The second and third values are pre-selected to test selector circuits for stuck-at-faults with a pattern where the pattern includes a set of bits to be inputted to selector circuits and a set of bits to be stored in the memory cells. A value stored in the n-most significant bits in both the second and third registers may be predecoded to produce a predecode value. The predecode value may be compared with the value stored in the n-most significant bits in an entry in the memory array to determine a stuck-at-fault.
摘要翻译：一种用于测试故障故障的方法，计算机程序产品和系统。第一寄存器可以加载第一值，其中第一值可以被写入存储器阵列中的每个条目。第二个寄存器可以加载第二个值。第三个寄存器可以加载第二个值或第三个值。预先选择第二和第三值以使用模式测试选择器电路，其中模式包括要输入到选择器电路的一组位和要存储在存储器单元中的一组位。存储在第二和第三寄存器中的最高有效位中的值可以被预解码以产生预代码值。可以将预解码值与存储在阵列中的条目中的n个最高有效位中的值进行比较，以确定是否存在故障。

6. 发明授权

US07552413B2 System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model 有权
标题翻译：系统和计算机程序，用于通过模拟完整阵列模型中边缘单元的操作来验证阵列的性能
公开(公告)号：US07552413B2
公开(公告)日：2009-06-23
申请号：US12166811
申请日：2008-07-02
申请人： Vikas Agarwal , Michael Ju Hyeok Lee , Philip G. Shephard, III
发明人： Vikas Agarwal , Michael Ju Hyeok Lee , Philip G. Shephard, III
IPC分类号： G06F17/50 , G11C29/00
CPC分类号： G06F17/5022
摘要： A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
摘要翻译：通过模拟全阵列模型中边缘单元的操作来验证阵列的性能的系统和计算机程序减少了完整设计验证所需的计算时间。阵列的边缘单元（或阵列分割的每个子阵列）经受定时仿真，而阵列的中心单元在逻辑上被禁用，但保留在电路模型中，从而提供适当的加载。如果计算指示由于非边缘单元造成的最坏情况，则指定额外的单元用于模拟。观察到字线到达以确定最坏情况行进行选择。对于写入操作，字边和数据边之间的差异用于定位任何非边缘“异常值”单元。对于读取操作，字线延迟与从边沿列数据确定的位线延迟相加以定位任何异常值。

7. 发明授权

US07424691B2 Method for verifying performance of an array by simulating operation of edge cells in a full array model 有权
标题翻译：通过模拟全阵列模型中边缘单元的操作来验证阵列的性能的方法
公开(公告)号：US07424691B2
公开(公告)日：2008-09-09
申请号：US11279312
申请日：2006-04-11
申请人： Vikas Agarwal , Michael Ju Hyeok Lee , Philip G. Shephard, III
发明人： Vikas Agarwal , Michael Ju Hyeok Lee , Philip G. Shephard, III
IPC分类号： G06F17/50 , G11C29/00
CPC分类号： G06F17/5022
摘要： A method for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
摘要翻译：通过模拟全阵列模型中边缘单元的操作来验证阵列的性能的方法减少了完整设计验证所需的计算时间。阵列的边缘单元（或阵列分割的每个子阵列）经受定时仿真，而阵列的中心单元在逻辑上被禁用，但保留在电路模型中，从而提供适当的加载。如果计算指示由于非边缘单元造成的最坏情况，则指定额外的单元用于模拟。观察到字线到达以确定最坏情况行进行选择。对于写入操作，字边和数据边之间的差异用于定位任何非边缘“异常值”单元。对于读取操作，字线延迟与从边沿列数据确定的位线延迟相加以定位任何异常值。

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