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1. 发明申请

US20090292963A1 Method and System for Testing an Electronic Circuit 失效
标题翻译：电子电路测试方法与系统
公开(公告)号：US20090292963A1
公开(公告)日：2009-11-26
申请号：US12123540
申请日：2008-05-20
申请人： Benjamin Robert Gass , Abel Alaniz , Asher Shlomo Lazarus , Timothy M. Skergan
发明人： Benjamin Robert Gass , Abel Alaniz , Asher Shlomo Lazarus , Timothy M. Skergan
IPC分类号： G06F11/27 , G06F11/25
CPC分类号： G06F11/27 , G01R31/318307 , G01R31/3187
摘要： A method for testing an electronic circuit comprises selecting a first log interval, a first log start pattern, a first log end pattern, and a first subset range of LBIST patterns from a plurality of LBIST patterns arranged in an order, wherein each LBIST pattern of the subset range of LBIST patterns causes an associated output of an electronic circuit. The method tests an electronic circuit in a first test by applying to the electronic circuit the first subset range of LBIST patterns sequentially in the order, thereby generating a first plurality of associated outputs. The method stores a first subset of associated outputs based on the first log interval, the first log start pattern, and the first log end pattern. The method compares the subset of associated outputs with known outputs to identify a first output mismatch.
摘要翻译：一种用于测试电子电路的方法包括从按顺序布置的多个LBIST图案中选择第一对数间隔，第一对数起始图案，第一日志结束图案和LBIST图案的第一子范围，其中每个LBIST图案 LBIST模式的子集范围导致电子电路的相关输出。该方法在第一次测试中通过以顺序向电子电路应用LBIST图案的第一子范围，从而产生第一多个相关联的输出，来测试电子电路。该方法基于第一日志间隔，第一日志开始模式和第一日志结束模式来存储关联输出的第一子集。该方法将相关输出的子集与已知输出进行比较，以识别第一输出失配。

2. 发明授权

US07418541B2 Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor 失效
标题翻译：用于间接访问内存映射资源的支持接口以减少带外支持处理器的系统连接的方法
公开(公告)号：US07418541B2
公开(公告)日：2008-08-26
申请号：US11055404
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
IPC分类号： G06F12/00 , G05B13/02 , G06F15/00 , G06F15/76
CPC分类号： G06F15/7842
摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.
摘要翻译：提供了一种用于存储器映射资源的支持接口的方法和装置。支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。内存映射支持接口更新内存，内存映射寄存器或内存映射资源。该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。系统还报告遇到的任何错误。

3. 发明授权

US06539491B1 Method and apparatus for implementing IEEE 1149.1 compliant boundary scan 失效
标题翻译：实现IEEE 1149.1兼容边界扫描的方法和装置
公开(公告)号：US06539491B1
公开(公告)日：2003-03-25
申请号：US09436111
申请日：1999-11-08
申请人： Timothy M. Skergan , Johnny J. LeBlanc
发明人： Timothy M. Skergan , Johnny J. LeBlanc
IPC分类号： G06F104
CPC分类号： G01R31/318552
摘要： A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock is synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip. During boundary scan, the pipelined controls are forced to static levels which are active levels for scanning. Non-pipelined signals control the boundary scan operation based directly on the TCK clock defined in the IEEE 1149.1 boundary scan standard.
摘要翻译：一种用于在芯片上流水线时钟控制信号的方法和装置。本发明通过允许通过流水线非扫描锁存器将时钟停止，扫描和调试的时钟控制分配到所有本地时钟缓冲器来避免对多个时钟分配系统的需要。测试控制流水线锁存器可以通过时钟接收器，中央时钟缓冲器和芯片的扇区缓冲器区域与时钟一起布线。可以使用相对低速的测试机构来驱动芯片的外部测试。测试时钟与芯片上的自由运行时钟同步，以允许电路在芯片测试期间以速度运行。在边界扫描期间，流水线控件被强制为静态级别，这些级别是扫描的有效级别。非流水线信号基于IEEE 1149.1边界扫描标准中定义的TCK时钟控制边界扫描操作。

4. 发明授权

US08734006B2 Calibration of an on-die thermal sensor 有权
标题翻译：校准片上热传感器
公开(公告)号：US08734006B2
公开(公告)日：2014-05-27
申请号：US13039037
申请日：2011-03-02
申请人： James M. Crafts , Joseph E. Dery , Timothy M. Skergan , Timothy C. Taylor
发明人： James M. Crafts , Joseph E. Dery , Timothy M. Skergan , Timothy C. Taylor
IPC分类号： G01K15/00 , G01K7/00
CPC分类号： G01K15/005 , G01K7/01
摘要： A method of calibrating a thermal sensor includes setting a wafer to a control temperature. The wafer includes the thermal sensor and other chip logic. The method also includes applying power exclusively to a thermal sensor circuit, calibrating the thermal sensor, and storing a calibration result. The method also includes retrieving the calibration result upon application of power to the other chip logic.
摘要翻译：校准热传感器的方法包括将晶片设置为控制温度。晶片包括热传感器和其他芯片逻辑。该方法还包括将功率专用于热传感器电路，校准热传感器以及存储校准结果。该方法还包括在向另一个芯片逻辑施加电力时检索校准结果。

5. 发明授权

US08090823B2 Providing low-level hardware access to in-band and out-of-band firmware 失效
标题翻译：提供对带内和带外固件的低级硬件访问
公开(公告)号：US08090823B2
公开(公告)日：2012-01-03
申请号：US12259942
申请日：2008-10-28
申请人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
IPC分类号： G06F15/173 , G06F15/167
CPC分类号： G06F15/161
摘要： Illustrative embodiments disclose a data processing system providing low-level hardware access to in-band and out-of-band firmware. The data processing system includes a plurality of chips that includes at least one processor chip and a plurality of support chips. At least one processor chip includes a field replaceable unit support interface master that uses a field replaceable unit support interface serial transmission protocol to communicate with the plurality of support chips. Each one of the plurality of support chips includes a field replaceable unit support interface slave in, with ones of the plurality of chips that include a processor also include the field replaceable unit support interface master, and ones of the plurality of chips that do not include the processor include only the field replaceable unit support interface slave. Only the field replaceable unit support interface master possesses conversion logic.
摘要翻译：说明性实施例公开了提供对带内和带外固件的低级硬件访问的数据处理系统。数据处理系统包括多个芯片，其包括至少一个处理器芯片和多个支持芯片。至少一个处理器芯片包括使用现场可更换单元支持接口串行传输协议与多个支持芯片进行通信的现场可更换单元支持接口主机。多个支持芯片中的每一个包括现场可更换单元支持接口从机，其中包括处理器的多个芯片中的一个包括现场可更换单元支持接口主机，以及不包括的多个芯片中的一个处理器仅包括现场可更换单元支持接口从站。只有现场可更换单元支持接口主机具有转换逻辑。

6. 发明授权

US07895490B2 Method and system for testing an electronic circuit to identify multiple defects 失效
标题翻译：用于测试电子电路以识别多个缺陷的方法和系统
公开(公告)号：US07895490B2
公开(公告)日：2011-02-22
申请号：US12123547
申请日：2008-05-20
申请人： Benjamin Robert Gass , Abel Alaniz , Asher Shlomo Lazarus , Timothy M. Skergan
发明人： Benjamin Robert Gass , Abel Alaniz , Asher Shlomo Lazarus , Timothy M. Skergan
IPC分类号： G01R31/28
CPC分类号： G06F11/27 , G01R31/318307 , G01R31/3187
摘要： A method for testing an electronic circuit comprises selecting a plurality of test patterns arranged in an order. The method tests an electronic circuit by applying to the electronic circuit a first subset range of the plurality of test patterns sequentially in the order, from a first test pattern to a first log interval after the first test pattern, thereby generating a first associated output. The method compares the first associated output with a first known output of the plurality of known outputs. In the event the first associated output does not match the first known output, the method stores indicia of the first mismatch; causes the electronic circuit to appear to assume the first known output state; and proceeds with additional test procedures.
摘要翻译：一种用于测试电子电路的方法包括选择按顺序布置的多个测试图案。该方法通过将电子电路中的多个测试图案的第一子集范围按顺序从第一测试图形顺序应用到第一测试图案之后的第一对数间隔，从而生成第一相关输出来测试电子电路。该方法将第一相关输出与多个已知输出的第一已知输出进行比较。在第一个相关联的输出与第一已知输出不匹配的情况下，该方法存储第一个不匹配的标记; 使电子电路看起来呈现第一已知输出状态; 并进行额外的测试程序。

7. 发明申请

US20090292964A1 Method and System for Testing an Electronic Circuit to Identify Multiple Defects 失效
标题翻译：用于测试电子电路以识别多个缺陷的方法和系统
公开(公告)号：US20090292964A1
公开(公告)日：2009-11-26
申请号：US12123547
申请日：2008-05-20
申请人： Benjamin Robert Gass , Abel Alaniz , Asher Shlomo Lazarus , Timothy M. Skergan
发明人： Benjamin Robert Gass , Abel Alaniz , Asher Shlomo Lazarus , Timothy M. Skergan
IPC分类号： G06F11/25 , G06F11/263
CPC分类号： G06F11/27 , G01R31/318307 , G01R31/3187
摘要： A method for testing an electronic circuit comprises selecting a plurality of test patterns arranged in an order. The method tests an electronic circuit by applying to the electronic circuit a first subset range of the plurality of test patterns sequentially in the order, from a first test pattern to a first log interval after the first test pattern, thereby generating a first associated output. The method compares the first associated output with a first known output of the plurality of known outputs. In the event the first associated output does not match the first known output, the method stores indicia of the first mismatch; causes the electronic circuit to appear to assume the first known output state; and proceeds with additional test procedures.
摘要翻译：一种用于测试电子电路的方法包括选择按顺序布置的多个测试图案。该方法通过将电子电路中的多个测试图案的第一子集范围按顺序从第一测试图形顺序应用到第一测试图案之后的第一对数间隔，从而生成第一相关输出来测试电子电路。该方法将第一相关输出与多个已知输出的第一已知输出进行比较。在第一个相关联的输出与第一已知输出不匹配的情况下，该方法存储第一个不匹配的标记; 使电子电路看起来呈现第一已知输出状态; 并进行额外的测试程序。

8. 发明授权

US6006311A Dynamic updating of repair mask used for cache defect avoidance 失效
标题翻译：用于缓存缺陷避免的修复掩码的动态更新
公开(公告)号：US6006311A
公开(公告)日：1999-12-21
申请号：US839559
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Timothy M. Skergan
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Timothy M. Skergan
IPC分类号： G06F13/00 , G11C29/00
CPC分类号： G11C29/88 , G06F12/126 , G11C29/76 , G06F2212/1032
摘要： A method of dynamically avoiding defective cache lines in a cache used by a processor of a computer system is disclosed. A repair mask is used, having an array of bit fields each corresponding to a cache lines in the cache, and certain bit fields in the repair mask array are initially set to indicate that a group of corresponding cache lines are defective. Thereafter the repair mask is updated by setting additional bit fields in the repair mask array to indicate that an additional group of corresponding cache lines are defective. Access to all defective cache lines is prevented based on the corresponding bit fields in the repair mask array. The initial setting of certain bit fields can take place at fabrication of the cache chip in response to testing of the cache lines. Additionally, the repair mask may be updated each time the computer system is booted in response to testing by the boot procedure. The repair mask may also be updated real-time during program execution in response to detection of an error associated with a particular cache line. Updating in real-time can be accomplished by counting a cumulative number of errors associated with a cache line, and then identifying the cache line as being defective only after a certain number of cumulative errors has occurred.
摘要翻译：公开了一种动态地避免由计算机系统的处理器使用的高速缓存中的有缺陷的高速缓存行的方法。使用具有每个对应于高速缓存中的高速缓存行的位字段阵列的修复掩码，并且初始设置修复掩码阵列中的某些位字段以指示一组对应的高速缓存行有缺陷。此后，通过在修复掩码阵列中设置附加位字段来指示修复掩码被更新以指示附加的一组对应的高速缓存行是有缺陷的。基于修复掩码阵列中的相应位字段来防止对所有有缺陷的高速缓存行的访问。响应于高速缓存行的测试，可以在制造高速缓存芯片时进行某些位字段的初始设置。此外，每当计算机系统引导时响应于引导过程的测试，可以更新修复掩码。响应于检测到与特定高速缓存行相关联的错误，修复掩码也可以在程序执行期间被实时更新。可以通过计数与高速缓存行相关联的错误的累积数量，然后将高速缓存行识别为在发生一定数量的累积错误之后的缺陷来实现。

9. 发明授权

US07916722B2 Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor 失效
标题翻译：用于间接访问内存映射资源的支持接口以减少带外支持处理器的系统连接的方法
公开(公告)号：US07916722B2
公开(公告)日：2011-03-29
申请号：US12139631
申请日：2008-06-16
申请人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
发明人： James Stephen Fields, Jr. , Paul Frank Lecocq , Brian Chan Monwai , Thomas Pflueger , Kevin Franklin Reick , Timothy M. Skergan , Scott Barnett Swaney
IPC分类号： H04L12/28 , H04L12/56 , H04L12/66 , G06F3/00 , G06F12/00
CPC分类号： G06F15/7842
摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.
摘要翻译：提供了一种用于存储器映射资源的支持接口的方法和装置。支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。内存映射支持接口更新内存，内存映射寄存器或内存映射资源。该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。结构命令转换为FSI协议，并转发到附加的支持芯片以访问存储器映射的资源，并且来自支持芯片的响应被转换回到结构响应分组。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。系统还报告遇到的任何错误。

10. 发明授权

US07856582B2 Techniques for logic built-in self-test diagnostics of integrated circuit devices 有权
标题翻译：逻辑内置自检诊断技术的集成电路设备
公开(公告)号：US07856582B2
公开(公告)日：2010-12-21
申请号：US12061752
申请日：2008-04-03
申请人： Daniel W. Cervantes , Robert B. Gass , Joshua P. Hernandez , Timothy M. Skergan
发明人： Daniel W. Cervantes , Robert B. Gass , Joshua P. Hernandez , Timothy M. Skergan
IPC分类号： G01R31/28 , G01R31/02 , G01R31/26
CPC分类号： G01R31/318335 , G01R31/3187 , G11C29/12015 , G11C29/16 , G11C29/44 , G11C2029/0405 , G11C2029/3202
摘要： A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded value (i.e., “signature” of the test cycle), the saved stump data and an identifier of the failed test cycle are preserved, otherwise the determination is made the DUT passed the test cycle. Identifiers and stump of the failed test cycles are used to analyze errors, including virtually non-reproducible errors.
摘要翻译：一种用于执行IC器件实时LBIST诊断的方法，系统和计算机程序产品。在LBIST期间，残留数据和测试周期的标识符保存在IC器件中（DUT）中。如果压缩树桩数据与预定义的编码值（即测试周期的“签名”）不匹配，则保存的桩号数据和故障测试周期的标识符被保留，否则确定DUT通过测试周期。故障测试周期的标识符和残差用于分析错误，包括几乎不可重现的错误。

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