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1. 发明授权

US5375091A Method and apparatus for memory dynamic burn-in and test 失效
标题翻译：用于记忆动态老化和测试的方法和装置
公开(公告)号：US5375091A
公开(公告)日：1994-12-20
申请号：US163803
申请日：1993-12-08
申请人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
发明人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
IPC分类号： G11C29/10 , G11C29/50 , G11C13/00
CPC分类号： G11C29/10 , G11C29/50
摘要： A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register. A plurality of independent circulating loops may be created in the data input register or in combination with a number of dummy register bits.
摘要翻译：嵌入在集成处理器芯片中的存储器通过重复地将测试图案写入存储器的数据位置而被动态地受到压力测试，其中高百分比的存储器单元被顺序地写有补充数据，以便在存储器上产生高应力设备。作为存储器的地址位置的数量和存储器数据字的数据位的数量的函数产生测试图案。每次存储器寻址时，测试模式都会旋转。测试图案优选地具有连续的数字组，连续组中的位数是作为存储器字中的地址位置数和数据位数的函数。存储器数据输入寄存器被配置为循环回路，并添加额外的虚拟位以提供比数据输入寄存器更长的再循环回路。可以在数据输入寄存器中或与多个虚拟寄存器位组合地产生多个独立的循环回路。

2. 发明授权

US5612963A Hybrid pattern self-testing of integrated circuits 失效
标题翻译：集成电路的混合模式自检
公开(公告)号：US5612963A
公开(公告)日：1997-03-18
申请号：US486100
申请日：1995-06-07
申请人： Bernd K. F. Koenemann , Kenneth D. Wagner , John A. Waicukauski
发明人： Bernd K. F. Koenemann , Kenneth D. Wagner , John A. Waicukauski
IPC分类号： G01R31/28 , G01R31/3181 , G01R31/3183 , G06F11/27
CPC分类号： G01R31/31813 , G01R31/318385 , G06F11/27
摘要： A hybrid random pattern self-test approach is employed in an on-chip fashion to provide desired test signals to circuits on the chip. A simplified weighting circuit is shown to be effective even when only a single bit from a linear feedback shift register is employed for random signal generation. The reduction in linear feedback shift register size and associated weighting circuitry enables the apparatus to be much more readily usable in an on-product configuration thus resulting in significant initial and subsequent test circuit advantages.
摘要翻译：混合随机模式自检方法以片上方式采用，以向芯片上的电路提供期望的测试信号。即使仅使用来自线性反馈移位寄存器的单个位来进行随机信号生成，简化的加权电路也被证明是有效的。线性反馈移位寄存器大小和相关加权电路的减少使得该装置能够更容易地用于产品配置，从而导致显着的初始和随后的测试电路优点。

3. 发明授权

US06169418A Efficient routing from multiple sources to embedded DRAM and other large circuit blocks 失效
标题翻译：从多个源到嵌入式DRAM和其他大型电路块的高效路由
公开(公告)号：US06169418A
公开(公告)日：2001-01-02
申请号：US09103757
申请日：1998-06-24
申请人： Kenneth D. Wagner
发明人： Kenneth D. Wagner
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1778
摘要： An improved routing system and method allow routing of pluralities of signals to circuit blocks on integrated circuit chips using minimal die area. The improved routing system employs a plurality of tri-state buffers, a plurality of conductive lines, and a controller. The circuit block can be driven from remote locations via the tri-state buffers and conductive lines. The tri-state buffers are selectively enabled one at a time by the controller to prevent signal contention. The multiplexors encountered in conventional routing systems are not needed. The improved routing system and method are ideal for routing to and from large circuit blocks which have numerous terminals, such as embedded dynamic random access memory units, embedded static random access memory units, central processing units, arithmetic logic units, register files, and cores generally. The improved routing system and method also allow testing of large circuit blocks with test vectors supplied by built in self test units and or off-chip test equipment.
摘要翻译：改进的路由系统和方法允许使用最小管芯区域将多个信号路由到集成电路芯片上的电路块。改进的路由系统采用多个三态缓冲器，多条导线以及控制器。电路块可以通过三态缓冲器和导线从远程位置驱动。三态缓冲器由控制器一次选择性地启用以防止信号争用。在传统路由系统中遇到的多路复用器不需要。改进的路由系统和方法非常适合用于路由到具有许多终端的大电路块的路由，例如嵌入式动态随机存取存储器单元，嵌入式静态随机存取存储器单元，中央处理单元，算术逻辑单元，寄存器文件和内核通常。改进的路由系统和方法还允许使用由内置自检单元和片外测试设备提供的测试向量来测试大电路块。

4. 发明授权

US6158033A Multiple input signature testing & diagnosis for embedded blocks in integrated circuits 失效
标题翻译：集成电路中嵌入式块的多输入签名测试与诊断
公开(公告)号：US6158033A
公开(公告)日：2000-12-05
申请号：US75350
申请日：1998-05-08
申请人： Kenneth D. Wagner , Mehran Amerian
发明人： Kenneth D. Wagner , Mehran Amerian
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318547 , G01R31/318505
摘要： An integrated circuit includes a first circuit module for generating a plurality of digital signals and a second circuit module for receiving the digital signals. A multiple input signature module receives the digital signals that are received by the second circuit module. The signature module generates and stores a signature value which is indicative of data values of the digital signals over a plurality of cycles. The signature module operates in response to control circuitry, which is responsive to a test signal, to cause the values indicative of the digital signals to be stored to the multiple input signature module, each time that valid signal values are received by the second circuit module. The multiple input signature module may be used for diagnostics by capturing data at a single, predetermined cycle. The module may be initialized to a predetermined value to ensure the signature value or, the single value captured, accurately reflects the data value of the digital signals. The control circuitry is further responsive to a signature data signal for causing data stored in the multiple input signature module to be provided on at least a first output pin of the integrated circuit. The integrated circuit includes scan circuitry and the signature data signal causes the multiple input signature module to form a portion of the scan circuitry.
摘要翻译：集成电路包括用于产生多个数字信号的第一电路模块和用于接收数字信号的第二电路模块。多输入签名模块接收由第二电路模块接收的数字信号。签名模块生成并存储表示多个周期的数字信号的数据值的签名值。每当有效信号值被第二电路模块接收时，签名模块响应于响应于测试信号的控制电路而操作，以使得指示数字信号的值被存储到多输入签名模块。多输入签名模块可以通过以单个预定周期捕获数据来用于诊断。模块可以被初始化为预定值，以确保签名值或所捕获的单个值准确地反映数字信号的数据值。所述控制电路还响应于签名数据信号，以使存储在所述多输入签名模块中的数据提供在所述集成电路的至少第一输出引脚上。集成电路包括扫描电路，签名数据信号使多输入签名模块形成扫描电路的一部分。

5. 发明授权

US5633812A Fault simulation of testing for board circuit failures 失效
标题翻译：板电路故障测试故障模拟
公开(公告)号：US5633812A
公开(公告)日：1997-05-27
申请号：US953396
申请日：1992-09-29
申请人： James S. Allen , Theresa L. Meyer , Kenneth D. Wagner
发明人： James S. Allen , Theresa L. Meyer , Kenneth D. Wagner
IPC分类号： G01R31/3183 , G06F11/00
CPC分类号： G01R31/318342
摘要： A method of accurately simulating how design defects and faults are detected in the board design and manufacturing test environments is provided which uses statements in the simulation control language of a fault simulator. The simulation of the operation of electronic boards (which may not yet have been built) in their expected test environments is possible. The set of statements used in the simulation language allows the proposed functional self-test code, also called diagnostic code or power-on self-test code, which is to be executed by a (micro-)processor, to be tested for its effectiveness. The simulation must synchronize the simulated execution of the processor code to be evaluated with the fault detection by the code being evaluated, simulate the use of any attached tester, such as a logic analyzer, and provide data that can be used for programming devices in the test environment. The PROBE statements in the simulation language determine when the simulator starts and ends a measurement window during which faults can be detected by the simulator. These statements can be used to simulate the amount of time a net must remain stable for test equipment to capture its value.
摘要翻译：提供了一种准确模拟板设计和制造测试环境中如何检测设计缺陷和故障的方法，其使用故障模拟器的仿真控制语言中的语句。在其预期的测试环境中模拟电子板的操作（可能尚未构建）是可能的。在仿真语言中使用的语句集合允许由微处理器执行的提出的功能自检代码（也称为诊断代码或开机自检代码）被测试其有效性。模拟必须使待评估的处理器代码的模拟执行与被评估的代码的故障检测同步，模拟任何附加的测试器（如逻辑分析仪）的使用，并提供可用于编程设备中的编程设备的数据测试环境。模拟语言中的PROBE语句确定模拟器何时启动和结束测量窗口，在此期间模拟器可以检测到故障。这些语句可用于模拟测试设备捕获其值的网络必须保持稳定的时间量。

6. 发明授权

US08843870B2 Method of reducing current leakage in a device and a device thereby formed 有权
标题翻译：减少装置和由此形成的装置中的电流泄漏的方法
公开(公告)号：US08843870B2
公开(公告)日：2014-09-23
申请号：US13535835
申请日：2012-06-28
申请人： Bruce Scatchard , Chunfang Xie , Scott Barrick , Kenneth D. Wagner
发明人： Bruce Scatchard , Chunfang Xie , Scott Barrick , Kenneth D. Wagner
IPC分类号： G06F17/50
CPC分类号： H01L21/823807 , H01L21/26513 , H01L21/823412 , H01L21/823418
摘要： A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation. The method can substantially increase the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The method is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for other unused circuits, such as a high Vt circuit, a standard Vt circuit, a low Vt circuit, and an SRAM cell Vt circuit.
摘要翻译：减少在半导体制造期间执行的未使用电路中的电流泄漏的方法以及由此形成的半导体器件或集成电路。该方法包括修改在产品变型中未使用的至少一个空闲电路的特性，以在供电以及在操作期间抑制电路并减少其电流泄漏。该方法可以显着增加给定类型的所有晶体管的Vt（阈值电压），例如所有N型晶体管或所有P型晶体管。该方法还适用于控制其他晶体管参数，例如晶体管沟道长度，以及其他有源元件，例如N型电阻器或P型电阻器，在影响漏电流的未使用电路中以及其他未使用的电路，例如高Vt电路，标准Vt电路，低Vt电路和SRAM单元Vt电路。

7. 发明授权

US06389566B1 Edge-triggered scan flip-flop and one-pass scan synthesis methodology 失效
标题翻译：边沿触发扫描触发器和一遍扫描合成方法
公开(公告)号：US06389566B1
公开(公告)日：2002-05-14
申请号：US09088754
申请日：1998-06-02
申请人： Kenneth D. Wagner , Srinivasan R. Iyengar , Mehran Amerian
发明人： Kenneth D. Wagner , Srinivasan R. Iyengar , Mehran Amerian
IPC分类号： G01R3128
CPC分类号： G01R31/318541
摘要： An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by providing a weak scan output signal driver and inserting delay elements within a cell for a scan flip-flop in the scan signal path. The use of the improved scan flip-flop allows for a one-pass scan synthesis process which provides accurate flip-flop cell timing and area information during the design process.
摘要翻译：改进的扫描触发器及其使用方法。扫描触发器具有由扫描输出信号驱动器驱动的单独的专用扫描输出。通过提供弱扫描输出信号驱动器并在扫描信号路径中的扫描触发器的单元内插入延迟元件来最小化扫描移位竞争条件。改进的扫描触发器的使用允许在设计过程中提供准确的触发器单元定时和区域信息的单遍扫描合成处理。

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