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1. 发明授权

US07139995B1 Integration of a run-time parameterizable core with a static circuit design 有权
标题翻译：集成一个运行时参数化的核心与静态电路设计
公开(公告)号：US07139995B1
公开(公告)日：2006-11-21
申请号：US10102585
申请日：2002-03-19
申请人： Philip B. James-Roxby , Daniel J. Downs , Russell J. Morgan , Cameron D. Patterson
发明人： Philip B. James-Roxby , Daniel J. Downs , Russell J. Morgan , Cameron D. Patterson
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F17/5054
摘要： Method and apparatus for integrating a run-time parameterizable logic core with a static circuit design. A configuration bitstream is generated from a main circuit design that is specified in a hardware description language. The main circuit design includes a first sub-circuit design that specifies a selected subset of resources of the PLD needed by the RTP core and an interface between the RTP core and other parts of the main circuit design. Via execution of a run-time reconfiguration control program, the configuration data that correspond to the first sub-circuit design are replaced with configuration data that implement the RTP core. The run-time reconfiguration program then configures the PLD with the updated configuration bitstream.
摘要翻译：用于将运行时参数化逻辑核与静态电路设计集成的方法和装置。从硬件描述语言指定的主电路设计中生成配置比特流。主电路设计包括第一子电路设计，其指定RTP核心所需的PLD的所选资源子集以及RTP核心与主电路设计的其他部分之间的接口。通过执行运行时重新配置控制程序，将与第一子电路设计相对应的配置数据替换为实施RTP核心的配置数据。运行时重新配置程序然后使用更新的配置比特流配置PLD。

2. 发明授权

US06621295B1 Reconfigurable priority encoding 有权
标题翻译：可重新配置的优先级编码
公开(公告)号：US06621295B1
公开(公告)日：2003-09-16
申请号：US10047667
申请日：2002-01-15
申请人： Philip B. James-Roxby , Daniel J. Downs
发明人： Philip B. James-Roxby , Daniel J. Downs
IPC分类号： G06F738
CPC分类号： G06F7/74
摘要： A reconfigurable priority encoding arrangement and method. In various embodiments, the invention identifies, from a plurality of input signals, a highest priority signal that is in a selected state. A priority routing block is implemented on a programmable logic device (PLD). The routing block has a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports. A priority encoder is also implemented on the PLD and has input ports respectively coupled to the output ports of the priority routing block. Each input port has a priority relative to others of the input ports. The priority encoder is configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state.
摘要翻译：可重构优先级编码方案。在各种实施例中，本发明从多个输入信号中识别处于选定状态的最高优先级信号。优先级路由块在可编程逻辑器件（PLD）上实现。路由块具有布置成接收相应输入信号的多个输入端口和分别耦合到输入端口的多个输出端口。优先编码器也在PLD上实现，并且具有分别耦合到优先级路由块的输出端口的输入端口。每个输入端口相对于其他输入端口具有优先级。优先编码器被配置为生成识别具有最高优先级并且处于选择状态的输入信号的地址信号。

3. 发明授权

US07627291B1 Integrated circuit having a routing element selectively operable to function as an antenna 有权
标题翻译：集成电路具有选择性地可操作地用作天线的路由元件
公开(公告)号：US07627291B1
公开(公告)日：2009-12-01
申请号：US11040133
申请日：2005-01-21
申请人： Philip B. James-Roxby , Daniel J. Downs
发明人： Philip B. James-Roxby , Daniel J. Downs
IPC分类号： H04B1/38
CPC分类号： H01Q1/44 , H01Q1/2283
摘要： An integrated circuit operable to wirelessly communicate with other devices by utilizing a radio transceiver and a routing element is disclosed. The routing element is operable to route a signal between various circuit elements and is selectively operable to function as an antenna when coupled with the radio transceiver.
摘要翻译：公开了一种可通过利用无线电收发器和路由元件与其他设备进行无线通信的集成电路。路由元件可操作以在各种电路元件之间路由信号，并且当与无线电收发器耦合时可选择性地操作以用作天线。

4. 发明授权

US07171644B1 Implementation set-based guide engine and method of implementing a circuit design 有权
标题翻译：实现集导向引擎和实现电路设计的方法
公开(公告)号：US07171644B1
公开(公告)日：2007-01-30
申请号：US10912957
申请日：2004-08-06
申请人： John J. Laurence , Daniel J. Downs , Raymond Kong , Richard Yachyang Sun
发明人： John J. Laurence , Daniel J. Downs , Raymond Kong , Richard Yachyang Sun
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing directives on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of creating and depositing tasks on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of invoking each task deposited on guide implementation set nodes as each node in the guide implementation set tree is visited.
摘要翻译：实现集成电路设计的方法可以包括形成基本实现集合并形成具有多个指导实施集节点的指导实现集的步骤。该方法还可以包括以下步骤：在多个指导实施集节点中的至少一个引导实施集节点（或每个节点）上存储指令。该方法还可以包括以下步骤：在多个指导实施集节点中的至少一个指导实施集节点（或每个节点）上创建和存储任务。该方法还可以包括在引导实现集树中的每个节点被访问时调用在指导实现集合节点上存储的每个任务的步骤。

5. 发明授权

US08141010B1 Method and arrangement providing for implementation granularity using implementation sets 有权
公开(公告)号：US08141010B1
公开(公告)日：2012-03-20
申请号：US12028337
申请日：2008-02-08
申请人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasan
发明人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

6. 发明授权

US07290241B1 Method and system for managing behavior of algorithms 有权
标题翻译：用于管理算法行为的方法和系统
公开(公告)号：US07290241B1
公开(公告)日：2007-10-30
申请号：US10913752
申请日：2004-08-06
申请人： Daniel J. Downs , John D. Bunte , Raymond Kong , John J. Laurence , Richard Yachyang Sun
发明人： Daniel J. Downs , John D. Bunte , Raymond Kong , John J. Laurence , Richard Yachyang Sun
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of managing behavior of algorithms includes specifying governing rules/policies that manage I-Set implementation directives, command line options, and environment variables and loading governing rules/policies into a behavior manager. Inside a client tool, the I-Set hierarchy processes and iterates one I-Set node at a time. Without more I-Sets to process, the method is done. If more, then the tool queries the Behavior Manager with an I-Set with symbolic designators of the queried behavior. The Behavior Manager can reply to the client tool indicating whether the queried behavior is to be supported on the appropriate logic of the I-Set node. If the algorithm for the I-Set node lacks the queried behavior, then another I-Set might require processing. If the algorithm for the I-Set node has the queried behavior, then the client tool applies the corresponding algorithm(s) on the appropriate logic.
摘要翻译：一种管理算法行为的方法包括指定管理I-Set实现指令，命令行选项和环境变量的管理规则/策略，并将管理规则/策略加载到行为管理器中。在客户端工具中，I-Set层次结构一次处理并迭代一个I-Set节点。没有更多的I-Sets要处理，该方法就完成了。如果更多，那么该工具将使用具有查询行为的符号指示符的I-Set查询“行为管理器”。行为管理器可以回复客户端工具，指示是否在I-Set节点的相应逻辑上支持查询行为。如果I-Set节点的算法缺少查询行为，则另一个I-Set可能需要处理。如果I-Set节点的算法具有查询行为，则客户端工具将相应的算法应用于适当的逻辑。

7. 发明授权

US07360177B1 Method and arrangement providing for implementation granularity using implementation sets 有权
标题翻译：使用实现集提供实现粒度的方法和布置
公开(公告)号：US07360177B1
公开(公告)日：2008-04-15
申请号：US10913000
申请日：2004-08-06
申请人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasan
发明人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.
摘要翻译：基于用于集成电路设计的用户设计的实现集抽象的设计层次结构包括多个节点和多个节点中的每个节点的定义，其描述了包含在每个节点中的元素的类型和所定义的层级通过每个节点。每个节点可以包括设计的至少一个实现元素，并且可以在包括一组逻辑元素，一组放置元素以及一组放置和路由元素的组中选择该至少一个实现元素。

8. 发明授权

US07181704B1 Method and system for designing integrated circuits using implementation directives 有权
标题翻译：使用实施指令设计集成电路的方法和系统
公开(公告)号：US07181704B1
公开(公告)日：2007-02-20
申请号：US10913746
申请日：2004-08-06
申请人： Daniel J. Downs , Raymond Kong , John J. Laurence , Sankaranarayanan Srinivasan , Richard Yachyang Sun
发明人： Daniel J. Downs , Raymond Kong , John J. Laurence , Sankaranarayanan Srinivasan , Richard Yachyang Sun
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of designing an integrated circuit using implementation directives for flow control can include the step of loading a design along with specified constraints, creating at least one instance of an data structure formed from a partial netlist, and decomposing at least one set of high level rules into simple implementation directives. The method can further include the steps of selectively attaching the simple implementation directives to the data structure, implementing a task manager which queries a data structure node to create a list of tasks to be performed on the data structure, and executing the list of tasks using a generic flow engine.
摘要翻译：使用用于流量控制的实施指令来设计集成电路的方法可以包括加载设计以及指定约束的步骤，创建由部分网表形成的数据结构的至少一个实例，并且分解至少一组高级别规则到简单的实施指令。该方法还可以包括以下步骤：将简单实施指令有选择地附加到数据结构，实现查询数据结构节点以创建要在数据结构上执行的任务列表的任务管理器，以及使用通用流引擎。

9. 发明授权

US06351143B1 Content-addressable memory implemented using programmable logic 有权
标题翻译：使用可编程逻辑实现的可内容寻址存储器
公开(公告)号：US06351143B1
公开(公告)日：2002-02-26
申请号：US09882615
申请日：2001-06-15
申请人： Steven A. Guccione , Delon Levi , Daniel J. Downs
发明人： Steven A. Guccione , Delon Levi , Daniel J. Downs
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： Described are systems and methods that take advantage of the run-time reconfigurability of modern programmable logic devices to efficiently implement content-addressable memory (CAM) circuits. Rather than using configurable logic to compare CAM entries stored in flip-flops, a CAM in accordance with the invention uses configurable logic for both data storage and comparison. A CAM in accordance with one embodiment of the invention includes a number of programmable look-up tables on a programmable logic device collectively configured to produce a “match” signal in response to data provided on a series of data input terminals. Configuration data determines the particular pattern to which the CAM responds, so new CAM entries are introduced by configuring (or reconfiguring) one or more of the look-up tables. A processor connected to the PLD responds to new CAM entries by executing instructions that first translate the new CAM entries into configuration data and then employ the configuration data to reprogram the PLD.
摘要翻译：描述了利用现代可编程逻辑器件的运行时可重构性来有效地实现内容寻址存储器（CAM）电路的系统和方法。不是使用可配置逻辑来比较存储在触发器中的CAM条目，根据本发明的CAM使用可配置的逻辑来进行数据存储和比较。根据本发明的一个实施例的CAM包括可编程逻辑设备上的多个可编程查找表，其被共同配置为响应于提供在一系列数据输入端上的数据而产生“匹配”信号。配置数据确定CAM响应的特定模式，因此通过配置（或重新配置）一个或多个查找表来引入新的CAM条目。连接到PLD的处理器通过执行首先将新的CAM条目转换成配置数据的指令来响应新的CAM条目，然后使用配置数据重新编程PLD。

10. 发明授权

US08296690B1 Method and arrangement providing for implementation granularity using implementation sets 有权
标题翻译：使用实现集提供实现粒度的方法和布置
公开(公告)号：US08296690B1
公开(公告)日：2012-10-23
申请号：US12027501
申请日：2008-02-07
申请人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasen
发明人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasen
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.
摘要翻译：基于用于集成电路设计的用户设计的实现集抽象的设计层次结构包括多个节点和多个节点中的每个节点的定义，其描述了包含在每个节点中的元素的类型和所定义的层级通过每个节点。每个节点可以包括设计的至少一个实现元素，并且可以在包括一组逻辑元素，一组放置元素以及一组放置和路由元素的组中选择该至少一个实现元素。

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