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1. 发明授权

US06278289B1 Content-addressable memory implemented using programmable logic 有权
标题翻译：使用可编程逻辑实现的可内容寻址存储器
公开(公告)号：US06278289B1
公开(公告)日：2001-08-21
申请号：US09562646
申请日：2000-05-01
申请人： Steven A. Guccione , Delon Levi , Daniel J. Downs
发明人： Steven A. Guccione , Delon Levi , Daniel J. Downs
IPC分类号： G06F738
CPC分类号： G11C15/00
摘要： Described are systems and methods that take advantage of the run-time reconfigurability of modern programmable logic devices to efficiently implement content-addressable memory (CAM) circuits. Rather than using configurable logic to compare CAM entries stored in flip-flops, a CAM in accordance with the invention uses configurable logic for both data storage and comparison. A CAM in accordance with one embodiment of the invention includes a number of programmable look-up tables on a programmable logic device collectively configured to produce a “match” signal in response to data provided on a series of data input terminals. Configuration data determines the particular pattern to which the CAM responds, so new CAM entries are introduced by configuring (or reconfiguring) one or more of the look-up tables. A processor connected to the PLD responds to new CAM entries by executing instructions that first translate the new CAM entries into configuration data and then employ the configuration data to reprogram the PLD.
摘要翻译：描述了利用现代可编程逻辑器件的运行时可重构性来有效地实现内容寻址存储器（CAM）电路的系统和方法。不是使用可配置逻辑来比较存储在触发器中的CAM条目，根据本发明的CAM使用可配置的逻辑来进行数据存储和比较。根据本发明的一个实施例的CAM包括可编程逻辑设备上的多个可编程查找表，其被共同配置为响应于提供在一系列数据输入端上的数据而产生“匹配”信号。配置数据确定CAM响应的特定模式，因此通过配置（或重新配置）一个或多个查找表来引入新的CAM条目。连接到PLD的处理器通过执行首先将新的CAM条目转换成配置数据的指令来响应新的CAM条目，然后使用配置数据重新编程PLD。

2. 发明授权

US06351143B1 Content-addressable memory implemented using programmable logic 有权
标题翻译：使用可编程逻辑实现的可内容寻址存储器
公开(公告)号：US06351143B1
公开(公告)日：2002-02-26
申请号：US09882615
申请日：2001-06-15
申请人： Steven A. Guccione , Delon Levi , Daniel J. Downs
发明人： Steven A. Guccione , Delon Levi , Daniel J. Downs
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： Described are systems and methods that take advantage of the run-time reconfigurability of modern programmable logic devices to efficiently implement content-addressable memory (CAM) circuits. Rather than using configurable logic to compare CAM entries stored in flip-flops, a CAM in accordance with the invention uses configurable logic for both data storage and comparison. A CAM in accordance with one embodiment of the invention includes a number of programmable look-up tables on a programmable logic device collectively configured to produce a “match” signal in response to data provided on a series of data input terminals. Configuration data determines the particular pattern to which the CAM responds, so new CAM entries are introduced by configuring (or reconfiguring) one or more of the look-up tables. A processor connected to the PLD responds to new CAM entries by executing instructions that first translate the new CAM entries into configuration data and then employ the configuration data to reprogram the PLD.
摘要翻译：描述了利用现代可编程逻辑器件的运行时可重构性来有效地实现内容寻址存储器（CAM）电路的系统和方法。不是使用可配置逻辑来比较存储在触发器中的CAM条目，根据本发明的CAM使用可配置的逻辑来进行数据存储和比较。根据本发明的一个实施例的CAM包括可编程逻辑设备上的多个可编程查找表，其被共同配置为响应于提供在一系列数据输入端上的数据而产生“匹配”信号。配置数据确定CAM响应的特定模式，因此通过配置（或重新配置）一个或多个查找表来引入新的CAM条目。连接到PLD的处理器通过执行首先将新的CAM条目转换成配置数据的指令来响应新的CAM条目，然后使用配置数据重新编程PLD。

3. 发明授权

US06487709B1 Run-time routing for programmable logic devices 有权
标题翻译：可编程逻辑器件的运行时路由
公开(公告)号：US06487709B1
公开(公告)日：2002-11-26
申请号：US09501356
申请日：2000-02-09
申请人： Eric R. Keller , Steven A. Guccione , Delon Levi
发明人： Eric R. Keller , Steven A. Guccione , Delon Levi
IPC分类号： G06F1750
CPC分类号： G06F17/5054 , H03K19/17752
摘要： A system and method for configuring routing resources of a programmable logic device are presented in various embodiments. In one embodiment, a first function is provided that automatically generates configuration bits for configuration of routing resources to connect a source to a sink. The input parameters to the to the first function include the source and the sink. A second function is provided to automatically generate configuration bits for configuration of routing resources that connect a source to a plurality of sinks. The second function is responsive to input parameters specifying the source and plurality of sinks. Additional program interfaces are provided and each provides various controls over the routing process.
摘要翻译：在各种实施例中呈现了用于配置可编程逻辑设备的路由资源的系统和方法。在一个实施例中，提供了第一功能，其自动地生成用于配置路由资源的配置位以将源连接到宿。到第一个功能的输入参数包括源和接收器。提供第二功能来自动生成用于配置将源连接到多个汇的路由资源的配置位。第二功能响应于指定源和多个汇的输入参数。提供了附加的程序接口，并且每个都提供了对路由进程的各种控制。

4. 发明授权

US06363519B1 Method and apparatus for testing evolvable configuration bitstreams 有权
标题翻译：用于测试可演化配置比特流的方法和装置
公开(公告)号：US06363519B1
公开(公告)日：2002-03-26
申请号：US09335422
申请日：1999-06-17
申请人： Delon Levi , Steven A. Guccione
发明人： Delon Levi , Steven A. Guccione
IPC分类号： G06F1750
CPC分类号： G06N3/126 , G06F17/5054
摘要： A system and method for evolving configuration bitstreams for a programmable logic device are disclosed. A plurality of data structures having respective sets of data are established. From the sets of data, respective configuration bitstreams are generated, wherein the sets of data are mapped to positions in the bitstreams. The configuration bitstreams are then evaluated for relative suitability to meet predetermined criteria when deployed on a programmable logic device. From the relative suitability of the configuration bitstreams, next-generation data for the data structures are generated using a genetic algorithm applied to sets of data. In the various embodiments, the configuration bitstreams eliminate resource contentions, selectively eliminate asynchronous behavior, include built-in test circuits, and are relocatable. Multiple populations of configuration bitstreams can evolve in parallel over a network.
摘要翻译：公开了用于演进用于可编程逻辑器件的配置比特流的系统和方法。建立具有各组数据的多个数据结构。从数据集合中，生成各自的配置比特流，其中数据集合被映射到比特流中的位置。然后，当部署在可编程逻辑器件上时，对配置比特流进行相对适合性的评估以满足预定标准。根据配置比特流的相对适用性，使用应用于数据集的遗传算法生成数据结构的下一代数据。在各种实施例中，配置比特流消除资源争用，选择性地消除异步行为，包括内置测试电路，并且是可重定位的。多个配置比特流群可以通过网络并行演进。

5. 发明授权

US06539532B1 Method and apparatus for relocating elements in an evolvable configuration bitstream 有权
标题翻译：用于在可演化配置比特流中重新定位元素的方法和装置
公开(公告)号：US06539532B1
公开(公告)日：2003-03-25
申请号：US09335437
申请日：1999-06-17
申请人： Delon Levi , Steven A. Guccione
发明人： Delon Levi , Steven A. Guccione
IPC分类号： G06F1750
CPC分类号： G06N3/126 , G06F17/5054
摘要： A system and method for evolving configuration bitstreams for a programmable logic device are disclosed. A plurality of data structures having respective sets of data are established. From the sets of data, respective configuration bitstreams are generated, wherein the sets of data are mapped to positions in the bitstreams. The configuration bitstreams are then evaluated for relative suitability to meet predetermined criteria when deployed on a programmable logic device. From the relative suitability of the configuration bitstreams, next-generation data for the data structures are generated using a genetic algorithm applied to sets of data. In the various embodiments, the configuration bitstreams eliminate resource contentions, selectively eliminate asynchronous behavior, include built-in test circuits, and are relocatable. Multiple populations of configuration bitstreams can evolve in parallel over a network.
摘要翻译：公开了用于演进用于可编程逻辑器件的配置比特流的系统和方法。建立具有各组数据的多个数据结构。从数据集合中，生成各自的配置比特流，其中数据集合被映射到比特流中的位置。然后，当部署在可编程逻辑器件上时，对配置比特流进行相对适合性的评估以满足预定标准。根据配置比特流的相对适用性，使用应用于数据集的遗传算法生成数据结构的下一代数据。在各种实施例中，配置比特流消除资源争用，选择性地消除异步行为，包括内置测试电路，并且是可重定位的。多个配置比特流群可以通过网络并行演进。

6. 发明授权

US06216259B1 Configuration of programmable logic devices with routing core generators 有权
标题翻译：配置可编程逻辑器件与路由核心发生器
公开(公告)号：US06216259B1
公开(公告)日：2001-04-10
申请号：US09168300
申请日：1998-10-07
申请人： Steven A. Guccione , Delon Levi
发明人： Steven A. Guccione , Delon Levi
IPC分类号： G06F1750
CPC分类号： G06F17/5054
摘要： A system and method for configuration of a programmable logic device using routing cores. A program executing on a processor includes instructions that select functions to be provided by the programmable logic device. The instructions invoke functions from a library of logic and router core generators to define logic cores and router cores to intercouple the logic cores. From the logic and router core definitions, the program utilizes a bit-stream library to generate programming bits. The programmable logic device is then loaded with the programming bits by the program.
摘要翻译：一种使用路由核心配置可编程逻辑器件的系统和方法。在处理器上执行的程序包括选择要由可编程逻辑器件提供的功能的指令。该指令调用逻辑库和路由器核心发生器的函数，以定义逻辑核心和路由器核心来互连逻辑核心。从逻辑和路由器核心定义，程序利用位流库生成编程位。然后可编程逻辑器件通过程序加载编程位。

7. 发明授权

US06430736B1 Method and apparatus for evolving configuration bitstreams 失效
标题翻译：用于演进配置比特流的方法和装置
公开(公告)号：US06430736B1
公开(公告)日：2002-08-06
申请号：US09335862
申请日：1999-06-17
申请人： Delon Levi , Steven A. Guccione
发明人： Delon Levi , Steven A. Guccione
IPC分类号： G06F1750
CPC分类号： G06N3/126 , G06F17/5054
摘要： A system and method for evolving configuration bitstreams for a programmable logic device are disclosed. A plurality of data structures having respective sets of data are established. From the sets of data, respective configuration bitstreams are generated, wherein the sets of data are mapped to positions in the bitstreams. The configuration bitstreams are then evaluated for relative suitability to meet predetermined criteria when deployed on a progammable logic device. From the relative suitability of the configuration bitstreams, next-generation data for the data structures are generated using a genetic algorithm applied to sets of data. In the various embodiments, the configuration bitstreams eliminate resource contentions, selectively eliminate asynchronous behavior, include built-in test circuits, and are relocatable. Multiple populations of configuration bitstreams can evolve in parallel over a network.
摘要翻译：公开了用于演进用于可编程逻辑器件的配置比特流的系统和方法。建立具有各组数据的多个数据结构。从数据集合中，生成各自的配置比特流，其中数据集合被映射到比特流中的位置。然后，当部署在可程序逻辑器件上时，将对相应的适配性进行评估以满足预定标准。根据配置比特流的相对适用性，使用应用于数据集的遗传算法生成数据结构的下一代数据。在各种实施例中，配置比特流消除资源争用，选择性地消除异步行为，包括内置测试电路，并且是可重定位的。多个配置比特流群可以通过网络并行演进。

8. 发明授权

US06378122B1 Method and apparatus for evolving a plurality of versions of a configuration bitstream in parallel 有权
标题翻译：用于并行地演进配置比特流的多个版本的方法和装置
公开(公告)号：US06378122B1
公开(公告)日：2002-04-23
申请号：US09336423
申请日：1999-06-17
申请人： Delon Levi , Steven A. Guccione
发明人： Delon Levi , Steven A. Guccione
IPC分类号： G06F1750
CPC分类号： G06N3/126 , G06F17/5054
摘要： A system and method for evolving configuration bitstreams for a programmable logic device are disclosed. A plurality of data structures having respective sets of data are established. From the sets of data, respective configuration bitstreams are generated, wherein the sets of data are mapped to positions in the bitstreams. The configuration bitstreams are then evaluated for relative suitability to meet predetermined criteria when deployed on a programmable logic device. From the relative suitability of the configuration bitstreams, next-generation data for the data structures are generated using a genetic algorithm applied to sets of data. In the various embodiments, the configuration bitstreams eliminate resource contentions, selectively eliminate asynchronous behavior, include built-in test circuits, and are relocatable. Multiple populations of configuration bitstreams can evolve in parallel over a network.
摘要翻译：公开了用于演进用于可编程逻辑器件的配置比特流的系统和方法。建立具有各组数据的多个数据结构。从数据集合中，生成各自的配置比特流，其中数据集合被映射到比特流中的位置。然后，当部署在可编程逻辑器件上时，对配置比特流进行相对适合性的评估以满足预定标准。根据配置比特流的相对适用性，使用应用于数据集的遗传算法生成数据结构的下一代数据。在各种实施例中，配置比特流消除资源争用，选择性地消除异步行为，包括内置测试电路，并且是可重定位的。多个配置比特流群可以通过网络并行演进。

9. 发明授权

US06363517B1 Method and apparatus for remotely evolving configuration bitstreams 有权
标题翻译：用于远程演进配置比特流的方法和装置
公开(公告)号：US06363517B1
公开(公告)日：2002-03-26
申请号：US09335424
申请日：1999-06-17
申请人： Delon Levi , Steven A. Guccione
发明人： Delon Levi , Steven A. Guccione
IPC分类号： G06F1750
CPC分类号： G06F17/5054 , G06N3/126
摘要： A system and method for evolving configuration bitstreams for a programmable logic device are disclosed. A plurality of data structures having respective sets of data are established. From the sets of data, respective configuration bitstreams are generated, wherein the sets of data are mapped to positions in the bitstreams. The configuration bitstreams are then evaluated for relative suitability to meet predetermined criteria when deployed on a programmable logic device. From the relative suitability of the configuration bitstreams, next-generation data for the data structures are generated using a genetic algorithm applied to sets of data. In the various embodiments, the configuration bitstreams eliminate resource contentions, selectively eliminate asynchronous behavior, include built-in test circuits, and are relocatable. Multiple populations of configuration bitstreams can evolve in parallel over a network.
摘要翻译：公开了用于演进用于可编程逻辑器件的配置比特流的系统和方法。建立具有各组数据的多个数据结构。从数据集合中，生成各自的配置比特流，其中数据集合被映射到比特流中的位置。然后，当部署在可编程逻辑器件上时，对配置比特流进行相对适合性的评估以满足预定标准。根据配置比特流的相对适用性，使用应用于数据集的遗传算法生成数据结构的下一代数据。在各种实施例中，配置比特流消除资源争用，选择性地消除异步行为，包括内置测试电路，并且是可重定位的。多个配置比特流群可以通过网络并行演进。

10. 发明授权

US06922665B1 Method and system for device-level simulation of a circuit design for a programmable logic device 有权
标题翻译：用于可编程逻辑器件的电路设计的器件级仿真的方法和系统
公开(公告)号：US06922665B1
公开(公告)日：2005-07-26
申请号：US09757404
申请日：2001-01-08
申请人： Steven A. Guccione , Scott P. McMillan , Brandon J. Blodget
发明人： Steven A. Guccione , Scott P. McMillan , Brandon J. Blodget
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5022
摘要： A method and system for simulating a circuit design for a programmable logic device (PLD) at the device level. The same configuration data that is used to configure a PLD is used to generate objects that represent configurable logic elements of the PLD. During simulation, events are generated based on changes in output signal states of the objects. Each event includes an input signal state and identifies an object to which the input signal is to be applied. Since configurable logic elements are simulated, for example, lookup tables, instead of logic gates, fewer events need to be generated and processed than in a conventional simulator. In another embodiment, the system supports an interface that allows tools to interface with the simulator in the same manner as the tools interface with a PLD.
摘要翻译：一种用于在器件级模拟可编程逻辑器件（PLD）的电路设计的方法和系统。用于配置PLD的相同配置数据用于生成表示PLD的可配置逻辑元素的对象。在仿真期间，根据对象输出信号状态的变化生成事件。每个事件包括输入信号状态，并且识别输入信号要被施加到的对象。由于模拟可配置的逻辑元件，例如，查找表而不是逻辑门，需要比传统的模拟器更少的事件被生成和处理。在另一个实施例中，系统支持允许工具以与工具与PLD接口相同的方式与模拟器进行接口的接口。

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