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1. 发明授权

US07139995B1 Integration of a run-time parameterizable core with a static circuit design 有权
标题翻译：集成一个运行时参数化的核心与静态电路设计
公开(公告)号：US07139995B1
公开(公告)日：2006-11-21
申请号：US10102585
申请日：2002-03-19
申请人： Philip B. James-Roxby , Daniel J. Downs , Russell J. Morgan , Cameron D. Patterson
发明人： Philip B. James-Roxby , Daniel J. Downs , Russell J. Morgan , Cameron D. Patterson
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F17/5054
摘要： Method and apparatus for integrating a run-time parameterizable logic core with a static circuit design. A configuration bitstream is generated from a main circuit design that is specified in a hardware description language. The main circuit design includes a first sub-circuit design that specifies a selected subset of resources of the PLD needed by the RTP core and an interface between the RTP core and other parts of the main circuit design. Via execution of a run-time reconfiguration control program, the configuration data that correspond to the first sub-circuit design are replaced with configuration data that implement the RTP core. The run-time reconfiguration program then configures the PLD with the updated configuration bitstream.
摘要翻译：用于将运行时参数化逻辑核与静态电路设计集成的方法和装置。从硬件描述语言指定的主电路设计中生成配置比特流。主电路设计包括第一子电路设计，其指定RTP核心所需的PLD的所选资源子集以及RTP核心与主电路设计的其他部分之间的接口。通过执行运行时重新配置控制程序，将与第一子电路设计相对应的配置数据替换为实施RTP核心的配置数据。运行时重新配置程序然后使用更新的配置比特流配置PLD。

2. 发明授权

US06621295B1 Reconfigurable priority encoding 有权
标题翻译：可重新配置的优先级编码
公开(公告)号：US06621295B1
公开(公告)日：2003-09-16
申请号：US10047667
申请日：2002-01-15
申请人： Philip B. James-Roxby , Daniel J. Downs
发明人： Philip B. James-Roxby , Daniel J. Downs
IPC分类号： G06F738
CPC分类号： G06F7/74
摘要： A reconfigurable priority encoding arrangement and method. In various embodiments, the invention identifies, from a plurality of input signals, a highest priority signal that is in a selected state. A priority routing block is implemented on a programmable logic device (PLD). The routing block has a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports. A priority encoder is also implemented on the PLD and has input ports respectively coupled to the output ports of the priority routing block. Each input port has a priority relative to others of the input ports. The priority encoder is configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state.
摘要翻译：可重构优先级编码方案。在各种实施例中，本发明从多个输入信号中识别处于选定状态的最高优先级信号。优先级路由块在可编程逻辑器件（PLD）上实现。路由块具有布置成接收相应输入信号的多个输入端口和分别耦合到输入端口的多个输出端口。优先编码器也在PLD上实现，并且具有分别耦合到优先级路由块的输出端口的输入端口。每个输入端口相对于其他输入端口具有优先级。优先编码器被配置为生成识别具有最高优先级并且处于选择状态的输入信号的地址信号。

3. 发明授权

US07627291B1 Integrated circuit having a routing element selectively operable to function as an antenna 有权
标题翻译：集成电路具有选择性地可操作地用作天线的路由元件
公开(公告)号：US07627291B1
公开(公告)日：2009-12-01
申请号：US11040133
申请日：2005-01-21
申请人： Philip B. James-Roxby , Daniel J. Downs
发明人： Philip B. James-Roxby , Daniel J. Downs
IPC分类号： H04B1/38
CPC分类号： H01Q1/44 , H01Q1/2283
摘要： An integrated circuit operable to wirelessly communicate with other devices by utilizing a radio transceiver and a routing element is disclosed. The routing element is operable to route a signal between various circuit elements and is selectively operable to function as an antenna when coupled with the radio transceiver.
摘要翻译：公开了一种可通过利用无线电收发器和路由元件与其他设备进行无线通信的集成电路。路由元件可操作以在各种电路元件之间路由信号，并且当与无线电收发器耦合时可选择性地操作以用作天线。

4. 发明授权

US08032874B1 Generation of executable threads having source code specifications that describe network packets 有权
标题翻译：生成具有描述网络数据包的源代码规范的可执行线程
公开(公告)号：US08032874B1
公开(公告)日：2011-10-04
申请号：US11336163
申请日：2006-01-20
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F9/45 , G06F15/76
CPC分类号： G06F8/4434
摘要： From source code specification of each of a plurality of threads, those variables of a data structure referenced by the thread are determined. For each thread, a respective adaptation of the source code specification of the data structure is generated. Each adaptation includes only variables of the data structure that are referenced in the respective thread. The source code specifications of the threads are compiled into respective object code segments using the respective adaptations of the data structures. Each object code segment requires memory space for the data structure for only those variables included in the respective adaptation. The source code specification of the data structure describes a network packet, and the respective object code segments are configured to operate on the respective portions of the network packet stored in separate memories while executing on respective processors.
摘要翻译：根据多个线程中的每一个的源代码规范，确定线程引用的数据结构的那些变量。对于每个线程，生成数据结构的源代码规范的各自的适配。每个自适应仅包括在相应线程中引用的数据结构的变量。使用数据结构的相应修改，将线程的源代码规范编译成各自的对象代码段。每个目标代码段仅需要用于数据结构的存储器空间，用于仅包括在各自适配中的那些变量。数据结构的源代码规范描述了网络分组，并且相应的目标代码段被配置为在各个处理器上执行时在存储在单独存储器中的网络分组的各个部分上进行操作。

5. 发明授权

US07990867B1 Pipeline for processing network packets 有权
标题翻译：用于处理网络数据包的流水线
公开(公告)号：US07990867B1
公开(公告)日：2011-08-02
申请号：US11799860
申请日：2007-05-03
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G01R31/08
CPC分类号： H04L69/161
摘要： A pipeline is provided for processing network packets. The pipeline includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The look-ahead stage synchronizes two or more fields of a network packet. The operation stage modifies one or more of the fields of the network packet. The operation stage may modify state data and the fields of the network packet as a function of the state data and the fields. The insert/remove stage performs data insertion and removal at one or more fields of the network packet. The interleave stage ensures that the modified network packet follows rules for interleaving network packets. The look-ahead, operation, insert/remove, and interleave stages are generated from a textual language specification of the processing of the network packets by the pipeline.
摘要翻译：提供流水线来处理网络数据包。流水线包括一个预览阶段，一个操作阶段，一个插入/去除阶段和一个交错阶段。先行阶段同步网络数据包的两个或多个字段。操作阶段修改网络包的一个或多个字段。操作阶段可以根据状态数据和字段来修改状态数据和网络包的字段。插入/删除阶段在网络数据包的一个或多个字段执行数据插入和删除。交织阶段确保修改的网络分组遵循用于交织网络分组的规则。通过流水线对网络数据包的处理的文本语言规范生成前瞻，操作，插入/删除和交错阶段。

6. 发明授权

US07227378B2 Reconfiguration of a programmable logic device using internal control 有权
标题翻译：使用内部控制重新配置可编程逻辑器件
公开(公告)号：US07227378B2
公开(公告)日：2007-06-05
申请号：US11100971
申请日：2005-04-07
申请人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
发明人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
IPC分类号： G06F7/38
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17732 , H03K19/17756
摘要： A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.
摘要翻译：一种部分重新配置具有可编程模块的IC的方法，包括从配置存储器阵列读取配置信息的帧的步骤; 修改所述配置信息的至少一部分，从而创建修改的配置信息帧; 并用修改的帧覆盖配置存储器阵列中的配置信息的现有帧，由此部分地重新配置IC。

7. 发明授权

US06883147B1 Method and system for generating a circuit design including a peripheral component connected to a bus 有权
标题翻译：用于产生包括连接到总线的外围组件的电路设计的方法和系统
公开(公告)号：US06883147B1
公开(公告)日：2005-04-19
申请号：US10304471
申请日：2002-11-25
申请人： Jonathan B. Ballagh , Roger Brent Milne , Jeffrey D. Stroomer , Eric R. Keller , L. James Hwang , Philip B. James-Roxby
发明人： Jonathan B. Ballagh , Roger Brent Milne , Jeffrey D. Stroomer , Eric R. Keller , L. James Hwang , Philip B. James-Roxby
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505
摘要： Method and system for generating an electronic circuit design. A first logic block is instantiated in the design in response to user input controls. The first logic block includes parameters that specify its interface requirements. Bus interface blocks, which are parameterizable to connect a logic block to a bus, are provided in a library. Bus interface blocks that connect the first logic block to the bus are instantiated in the design, and the bus interface blocks are parameterized in response to the requirements of, the first logic block. The bus interface blocks are connected to the first logic block in such a way that the first logic block is extended into a peripheral that can communicate with the bus.
摘要翻译：用于生成电子电路设计的方法和系统。响应于用户输入控件，第一个逻辑块在设计中实例化。第一个逻辑块包括指定其接口要求的参数。在库中提供了可以将逻辑块连接到总线的总线接口块。在设计中实例化了将第一个逻辑块连接到总线的总线接口块，并根据第一个逻辑块的要求对总线接口块进行参数化。总线接口块以这样的方式连接到第一逻辑块，使得第一逻辑块被扩展到可以与总线通信的外设。

8. 发明授权

US08284772B1 Method for scheduling a network packet processor 有权
标题翻译：调度网络包处理器的方法
公开(公告)号：US08284772B1
公开(公告)日：2012-10-09
申请号：US11799953
申请日：2007-05-03
申请人： Philip B. James-Roxby , Eric R. Keller
发明人： Philip B. James-Roxby , Eric R. Keller
IPC分类号： H04L12/28 , H04L12/56 , G06F13/00 , G06F13/28 , G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F3/00 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method is provided for scheduling a network packet processor. A textual language specification is input of the processing of network packets by the network packet processor. The textual language specification includes memory read actions and modification actions. Each memory read action reads a stored value from a memory of the network packet processor. Each modification action modifies a field of the network packets. An availability is determined for each field read from the network packets for the memory read and modification actions. An availability is determined for each stored value read from the memory for the memory read actions. A look-ahead interval is determined from the availabilities. A respective storage class is determined for the fields for the memory read and modification actions. The respective storage class is one of a bus, a register, and a register with bypass.
摘要翻译：提供了一种用于调度网络分组处理器的方法。文本语言规范是网络分组处理器对网络分组处理的输入。文本语言规范包括内存读取操作和修改操作。每个存储器读取动作从网络数据包处理器的存储器读取存储的值。每个修改操作修改网络数据包的字段。确定从网络数据包读取的每个字段的存储器读取和修改动作的可用性。为存储器读取动作确定从存储器读取的每个存储值的可用性。从可用性确定预先间隔。为存储器读取和修改动作的字段确定相应的存储类别。相应的存储类是总线，寄存器和旁路寄存器之一。

9. 发明授权

US08122239B1 Method and apparatus for initializing a system configured in a programmable logic device 有权
标题翻译：用于初始化可编程逻辑器件中配置的系统的方法和装置
公开(公告)号：US08122239B1
公开(公告)日：2012-02-21
申请号：US12208452
申请日：2008-09-11
申请人： Philip B. James-Roxby , Stephen A. Neuendorffer , Henry E. Styles
发明人： Philip B. James-Roxby , Stephen A. Neuendorffer , Henry E. Styles
IPC分类号： G01R31/28 , G06F15/177 , G06F11/30 , G06F15/16 , G06F9/30 , G06F7/38
CPC分类号： H03K19/177
摘要： Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with first data; executing a first iteration of the system to process the first data; partially reconfiguring the PLD, during execution of the first iteration, to initialize shadow memory elements in the PLD with second data, the shadow memory elements respectively shadowing the memory elements in the system; transferring the second data from the shadow memory elements to the memory elements; and executing a second iteration of the system to process the second data.
摘要翻译：描述用于初始化可编程逻辑器件（PLD）中配置的系统的方法和装置。在一些示例中，该方法包括：利用第一数据初始化系统中的存储器元件; 执行所述系统的第一迭代以处理所述第一数据; 在第一次迭代的执行期间，部分地重新配置PLD以利用第二数据初始化PLD中的影子存储器元件，阴影存储器元件分别遮蔽系统中的存储器元件; 将所述第二数据从所述影子存储器元件传送到所述存储器元件; 以及执行所述系统的第二次迭代以处理所述第二数据。

10. 发明授权

US07823162B1 Thread circuits and a broadcast channel in programmable logic 有权
标题翻译：线程电路和可编程逻辑中的广播通道
公开(公告)号：US07823162B1
公开(公告)日：2010-10-26
申请号：US11067431
申请日：2005-02-25
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F9/54 , G06F17/50
CPC分类号： G06F17/5054
摘要： Embodiments of a message processing circuit are disclosed. In one embodiment, a high-level language is used to specify a broadcast channel and first and second thread circuits. The first thread circuit outputs messages to the broadcast channel, each message having units of data, and starts the second thread circuit, indicating position in a message at which the second thread circuit is to commence reading data. The broadcast channel receives messages from the first thread circuit and outputs data of each message along with a position code indicating position in the message of current output data. The second thread reads data from the broadcast channel at a specified position in a message. The high-level language specification is translated into a hardware description language (HDL) specification, and the HDL specification is used to generate configuration data for programmable logic. Programmable logic is configured to implement the thread circuits and broadcast channel.
摘要翻译：公开了一种消息处理电路的实施例。在一个实施例中，使用高级语言来指定广播频道以及第一和第二线程电路。第一线程电路将消息输出到广播信道，每个消息具有数据单元，并且启动第二线程电路，指示第二线程电路开始读取数据的消息中的位置。广播频道从第一线程电路接收消息，并输出每个消息的数据以及指示当前输出数据的消息中的位置的位置代码。第二个线程在消息中的指定位置从广播频道读取数据。高级语言规范被转换为硬件描述语言（HDL）规范，HDL规范用于生成可编程逻辑的配置数据。可编程逻辑被配置为实现线程电路和广播信道。

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