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1. 发明授权

US08032874B1 Generation of executable threads having source code specifications that describe network packets 有权
标题翻译：生成具有描述网络数据包的源代码规范的可执行线程
公开(公告)号：US08032874B1
公开(公告)日：2011-10-04
申请号：US11336163
申请日：2006-01-20
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F9/45 , G06F15/76
CPC分类号： G06F8/4434
摘要： From source code specification of each of a plurality of threads, those variables of a data structure referenced by the thread are determined. For each thread, a respective adaptation of the source code specification of the data structure is generated. Each adaptation includes only variables of the data structure that are referenced in the respective thread. The source code specifications of the threads are compiled into respective object code segments using the respective adaptations of the data structures. Each object code segment requires memory space for the data structure for only those variables included in the respective adaptation. The source code specification of the data structure describes a network packet, and the respective object code segments are configured to operate on the respective portions of the network packet stored in separate memories while executing on respective processors.
摘要翻译：根据多个线程中的每一个的源代码规范，确定线程引用的数据结构的那些变量。对于每个线程，生成数据结构的源代码规范的各自的适配。每个自适应仅包括在相应线程中引用的数据结构的变量。使用数据结构的相应修改，将线程的源代码规范编译成各自的对象代码段。每个目标代码段仅需要用于数据结构的存储器空间，用于仅包括在各自适配中的那些变量。数据结构的源代码规范描述了网络分组，并且相应的目标代码段被配置为在各个处理器上执行时在存储在单独存储器中的网络分组的各个部分上进行操作。

2. 发明授权

US07990867B1 Pipeline for processing network packets 有权
标题翻译：用于处理网络数据包的流水线
公开(公告)号：US07990867B1
公开(公告)日：2011-08-02
申请号：US11799860
申请日：2007-05-03
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G01R31/08
CPC分类号： H04L69/161
摘要： A pipeline is provided for processing network packets. The pipeline includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The look-ahead stage synchronizes two or more fields of a network packet. The operation stage modifies one or more of the fields of the network packet. The operation stage may modify state data and the fields of the network packet as a function of the state data and the fields. The insert/remove stage performs data insertion and removal at one or more fields of the network packet. The interleave stage ensures that the modified network packet follows rules for interleaving network packets. The look-ahead, operation, insert/remove, and interleave stages are generated from a textual language specification of the processing of the network packets by the pipeline.
摘要翻译：提供流水线来处理网络数据包。流水线包括一个预览阶段，一个操作阶段，一个插入/去除阶段和一个交错阶段。先行阶段同步网络数据包的两个或多个字段。操作阶段修改网络包的一个或多个字段。操作阶段可以根据状态数据和字段来修改状态数据和网络包的字段。插入/删除阶段在网络数据包的一个或多个字段执行数据插入和删除。交织阶段确保修改的网络分组遵循用于交织网络分组的规则。通过流水线对网络数据包的处理的文本语言规范生成前瞻，操作，插入/删除和交错阶段。

3. 发明授权

US07227378B2 Reconfiguration of a programmable logic device using internal control 有权
标题翻译：使用内部控制重新配置可编程逻辑器件
公开(公告)号：US07227378B2
公开(公告)日：2007-06-05
申请号：US11100971
申请日：2005-04-07
申请人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
发明人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
IPC分类号： G06F7/38
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17732 , H03K19/17756
摘要： A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.
摘要翻译：一种部分重新配置具有可编程模块的IC的方法，包括从配置存储器阵列读取配置信息的帧的步骤; 修改所述配置信息的至少一部分，从而创建修改的配置信息帧; 并用修改的帧覆盖配置存储器阵列中的配置信息的现有帧，由此部分地重新配置IC。

4. 发明授权

US06883147B1 Method and system for generating a circuit design including a peripheral component connected to a bus 有权
标题翻译：用于产生包括连接到总线的外围组件的电路设计的方法和系统
公开(公告)号：US06883147B1
公开(公告)日：2005-04-19
申请号：US10304471
申请日：2002-11-25
申请人： Jonathan B. Ballagh , Roger Brent Milne , Jeffrey D. Stroomer , Eric R. Keller , L. James Hwang , Philip B. James-Roxby
发明人： Jonathan B. Ballagh , Roger Brent Milne , Jeffrey D. Stroomer , Eric R. Keller , L. James Hwang , Philip B. James-Roxby
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505
摘要： Method and system for generating an electronic circuit design. A first logic block is instantiated in the design in response to user input controls. The first logic block includes parameters that specify its interface requirements. Bus interface blocks, which are parameterizable to connect a logic block to a bus, are provided in a library. Bus interface blocks that connect the first logic block to the bus are instantiated in the design, and the bus interface blocks are parameterized in response to the requirements of, the first logic block. The bus interface blocks are connected to the first logic block in such a way that the first logic block is extended into a peripheral that can communicate with the bus.
摘要翻译：用于生成电子电路设计的方法和系统。响应于用户输入控件，第一个逻辑块在设计中实例化。第一个逻辑块包括指定其接口要求的参数。在库中提供了可以将逻辑块连接到总线的总线接口块。在设计中实例化了将第一个逻辑块连接到总线的总线接口块，并根据第一个逻辑块的要求对总线接口块进行参数化。总线接口块以这样的方式连接到第一逻辑块，使得第一逻辑块被扩展到可以与总线通信的外设。

5. 发明授权

US08284772B1 Method for scheduling a network packet processor 有权
标题翻译：调度网络包处理器的方法
公开(公告)号：US08284772B1
公开(公告)日：2012-10-09
申请号：US11799953
申请日：2007-05-03
申请人： Philip B. James-Roxby , Eric R. Keller
发明人： Philip B. James-Roxby , Eric R. Keller
IPC分类号： H04L12/28 , H04L12/56 , G06F13/00 , G06F13/28 , G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F3/00 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method is provided for scheduling a network packet processor. A textual language specification is input of the processing of network packets by the network packet processor. The textual language specification includes memory read actions and modification actions. Each memory read action reads a stored value from a memory of the network packet processor. Each modification action modifies a field of the network packets. An availability is determined for each field read from the network packets for the memory read and modification actions. An availability is determined for each stored value read from the memory for the memory read actions. A look-ahead interval is determined from the availabilities. A respective storage class is determined for the fields for the memory read and modification actions. The respective storage class is one of a bus, a register, and a register with bypass.
摘要翻译：提供了一种用于调度网络分组处理器的方法。文本语言规范是网络分组处理器对网络分组处理的输入。文本语言规范包括内存读取操作和修改操作。每个存储器读取动作从网络数据包处理器的存储器读取存储的值。每个修改操作修改网络数据包的字段。确定从网络数据包读取的每个字段的存储器读取和修改动作的可用性。为存储器读取动作确定从存储器读取的每个存储值的可用性。从可用性确定预先间隔。为存储器读取和修改动作的字段确定相应的存储类别。相应的存储类是总线，寄存器和旁路寄存器之一。

6. 发明授权

US07823162B1 Thread circuits and a broadcast channel in programmable logic 有权
标题翻译：线程电路和可编程逻辑中的广播通道
公开(公告)号：US07823162B1
公开(公告)日：2010-10-26
申请号：US11067431
申请日：2005-02-25
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F9/54 , G06F17/50
CPC分类号： G06F17/5054
摘要： Embodiments of a message processing circuit are disclosed. In one embodiment, a high-level language is used to specify a broadcast channel and first and second thread circuits. The first thread circuit outputs messages to the broadcast channel, each message having units of data, and starts the second thread circuit, indicating position in a message at which the second thread circuit is to commence reading data. The broadcast channel receives messages from the first thread circuit and outputs data of each message along with a position code indicating position in the message of current output data. The second thread reads data from the broadcast channel at a specified position in a message. The high-level language specification is translated into a hardware description language (HDL) specification, and the HDL specification is used to generate configuration data for programmable logic. Programmable logic is configured to implement the thread circuits and broadcast channel.
摘要翻译：公开了一种消息处理电路的实施例。在一个实施例中，使用高级语言来指定广播频道以及第一和第二线程电路。第一线程电路将消息输出到广播信道，每个消息具有数据单元，并且启动第二线程电路，指示第二线程电路开始读取数据的消息中的位置。广播频道从第一线程电路接收消息，并输出每个消息的数据以及指示当前输出数据的消息中的位置的位置代码。第二个线程在消息中的指定位置从广播频道读取数据。高级语言规范被转换为硬件描述语言（HDL）规范，HDL规范用于生成可编程逻辑的配置数据。可编程逻辑被配置为实现线程电路和广播信道。

7. 发明授权

US07185309B1 Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip 有权
标题翻译：专用于可编程存储器架构和芯片上互连网络的方法和装置
公开(公告)号：US07185309B1
公开(公告)日：2007-02-27
申请号：US10769591
申请日：2004-01-30
申请人： Chidamber R. Kulkarni , Gordon J. Brebner , Eric R. Keller , Philip B. James-Roxby
发明人： Chidamber R. Kulkarni , Gordon J. Brebner , Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，接收包括存储器系统的属性的规范数据。响应于规范数据生成存储器系统的逻辑描述。逻辑描述定义了存储器组件和存储器互连组件。响应于逻辑描述生成存储器系统的物理描述。物理描述包括与由存储器组件定义的集成电路相关联的存储器电路。存储器电路包括由存储器互连部件定义的互连拓扑。

8. 发明授权

US07028283B1 Method of using a hardware library in a programmable logic device 有权
标题翻译：在可编程逻辑器件中使用硬件库的方法
公开(公告)号：US07028283B1
公开(公告)日：2006-04-11
申请号：US10354518
申请日：2003-01-30
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of using hardware libraries in a programmable logic device is disclosed. In particular, the method generally comprises steps of detecting a hardware library when compiling a software program for the programmable logic device; and accessing hardware module information stored in the hardware library; inserting the hardware module information of the hardware library into a reference platform.
摘要翻译：公开了一种在可编程逻辑器件中使用硬件库的方法。特别地，该方法通常包括以下步骤：当编译可编程逻辑器件的软件程序时检测硬件库; 以及访问硬件库中存储的硬件模块信息; 将硬件库的硬件模块信息插入参考平台。

9. 发明授权

US07792117B1 Method for simulating a processor of network packets 有权
标题翻译：用于模拟网络数据包处理器的方法
公开(公告)号：US07792117B1
公开(公告)日：2010-09-07
申请号：US11799966
申请日：2007-05-03
申请人： Eric R. Keller , Philip B. James-Roxby , Graham F. Schelle
发明人： Eric R. Keller , Philip B. James-Roxby , Graham F. Schelle
IPC分类号： H04L12/28
CPC分类号： H04L12/4633 , H04L49/901
摘要： A method is provided for simulating a processor of network packets. A specification is input for the processor. The specification includes actions specifying a modification of the network packets by the processor. Each action includes a guard condition that enables and disables the action. First and second values of certain fields are determined for each action. The guard condition enables and disables the action respectively for the first and second values of the fields. The network packets are generated. For each field included in the guard conditions, a value of the field is selected for each generated network packet from the values of the field within the first and second values for the actions. The specification of the processor is translated into a simulator of the processor. The modification of the network packets is simulated in the simulator. A result of the modification is displayed on a user interface.
摘要翻译：提供了一种用于模拟网络分组的处理器的方法。为处理器输入规格。该规范包括指定处理器对网络分组的修改的动作。每个动作包括启用和禁用操作的保护条件。确定每个动作的某些字段的第一个和第二个值。保护条件分别为字段的第一个和第二个值启用和禁用该操作。生成网络数据包。对于包括在保护条件中的每个字段，从动作的第一和第二值内的字段的值为每个生成的网络包选择字段的值。处理器的规格被转换成处理器的模拟器。在模拟器中模拟网络数据包的修改。修改的结果显示在用户界面上。

10. 发明授权

US07689726B1 Bootable integrated circuit device for readback encoding of configuration data 有权
标题翻译：可引导集成电路设备，用于配置数据的回读编码
公开(公告)号：US07689726B1
公开(公告)日：2010-03-30
申请号：US10956884
申请日：2004-10-01
申请人： Prasanna Sundararajan , Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Eric R. Keller
发明人： Prasanna Sundararajan , Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Eric R. Keller
IPC分类号： G06F3/00 , H03K19/173
CPC分类号： H03K19/17764 , G06F9/4401 , H03K19/17768
摘要： Method and apparatus for encoding configuration data is described. An integrated circuit device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the integrated circuit device via the configuration interface. The boot cores include a configuration encoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration encoder core provides a peripheral interface internal to the integrated circuit device, and the boot memory contains at least one set of instructions for encoding configuration data read from configuration memory. The encoded configuration data may be sent via the peripheral interface. Alternatively, configuration encoder core may include a configuration bitstream for instantiating an encoder in configurable resources for encoding readback configuration data.
摘要翻译：描述用于编码配置数据的方法和装置。具有配置接口的集成电路装置耦合到在配置接口处耦合的引导存储器。引导内存包含用于通过配置界面配置集成电路设备的引导内核。引导核心包括配置编码器内核和内部处理器接口核心。引导核心可以进一步包括处理器核心。配置编码器核心提供集成电路设备内部的外围接口，并且引导存储器包含用于对从配置存储器读取的配置数据进行编码的至少一组指令。编码的配置数据可以经由外设接口发送。或者，配置编码器核心可以包括配置比特流，用于在用于编码回读配置数据的可配置资源中实例化编码器。

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