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    • 1. 发明申请
    • Portable interconnection system for incompatible audio communication networks
    • 便携式互连系统,用于不兼容的音频通信网络
    • US20050195969A1
    • 2005-09-08
    • US10792479
    • 2004-03-03
    • Peter PflastererKenneth MarksRoger WilliamsDouglas HallJohn VanValkenburgh
    • Peter PflastererKenneth MarksRoger WilliamsDouglas HallJohn VanValkenburgh
    • H04B1/38H04M1/00H04M9/00
    • H04M9/002
    • A portable interconnection system has a housing having and a plurality of communications ports adapted for connection to a plurality of audio communication networks; electronics substantially enclosed by the housing; the electronics including at least interconnection electronics operative to selectively establish a plurality of independent connection sets, each connection set interconnecting at least a plurality of the communications ports for communications between a plurality of audio communication units operating in at least two different and incompatible ones of the audio communication networks; a user interface connected to the interconnection electronics and operative to control the interconnection electronics; wherein a combined weight of the housing and the electronics is not more than fifteen pounds. A display may show an interconnection status of the plurality of audio communication units for a plurality of the independent connection sets simultaneously.
    • 便携式互连系统具有壳体,其具有适于连接到多个音频通信网络的多个通信端口; 基本上被外壳包围的电子装置; 所述电子装置至少包括用于选择性地建立多个独立连接集的互连电子装置的互连电子装置,每个连接装置互连至少多个所述通信端口,以在多个音频通信单元之间进行通信,所述多个音频通信单元在至少两个不同的和不兼容的 音频通信网络; 连接到互连电子装置并用于控制互连电子装置的用户接口; 其中壳体和电子装置的组合重量不超过15磅。 显示器可以同时显示多个独立连接组的多个音频通信单元的互连状态。
    • 6. 发明申请
    • Method and device for joining jewelry components
    • 用于加入珠宝组件的方法和装置
    • US20070151294A1
    • 2007-07-05
    • US11305266
    • 2005-12-16
    • Roger Williams
    • Roger Williams
    • A44C7/00
    • A44C7/003
    • In accordance with one or more embodiments of the invention, a method of joining a decorative ornament to an earring base component includes a dapped piece (a meniscus lens shaped piece) of material joined to a threaded tube. An opening in the end of the tube connected to the dapped piece is aligned with a hole in the dapped piece. The support piece is then joined to a decorative ornament. The tube is threaded and receives a threaded rod-like base stud. The threaded base stud passes through the hole in the dapped piece and reaches the threads of the tube. The threaded tube provides alignment and increased support between the base stud and the decorative ornament.
    • 根据本发明的一个或多个实施例,将装饰装饰物连接到耳环底座部件的方法包括连接到螺纹管的材料的开孔件(弯月透镜形状件)。 连接到开孔的管的端部中的开口与开孔件中的孔对准。 然后将支撑件连接到装饰品上。 该管是带螺纹的并且接收一个螺纹杆状基座螺柱。 螺纹底座螺柱穿过开孔中的孔并到达管的螺纹。 螺纹管提供对准和增加的基部螺柱和装饰装饰之间的支撑。
    • 9. 发明授权
    • Electrically quantifying transistor spacer width
    • 电子量子化晶体管间隔物宽度
    • US06287877B1
    • 2001-09-11
    • US09668524
    • 2000-09-22
    • Roger WilliamsMark Brandon FuselierMichael Verne Fenske
    • Roger WilliamsMark Brandon FuselierMichael Verne Fenske
    • G01R3126
    • G01R31/275G01R31/2621
    • A method for electrically quantifying a semiconductor device's spacers' width. In one embodiment, a method comprises the step of measuring a resistance across a region of interest of each of a plurality of semiconductor structures including the semiconductor device in question, where the region of interest may be a source or drain region of the semiconductor structure or may be one of a plurality of lightly doped drain regions of the semiconductor structure. The method further comprises determining a width of one of a plurality of lightly doped drain regions of the semiconductor device from the resistance across the region of interest of each of the plurality of semiconductor structures. The method further comprises determining the semiconductor device's spacers' width from the width of one of the plurality of lightly doped drain regions of the semiconductor device.
    • 一种用于电化学半导体器件间隔物宽度的方法。 在一个实施例中,一种方法包括测量包括所讨论的半导体器件的多个半导体结构中的每一个的感兴趣区域的电阻的步骤,其中感兴趣区域可以是半导体结构的源极或漏极区域,或 可以是半导体结构的多个轻掺杂漏区中的一个。 该方法还包括从跨越多个半导体结构中的每一个的感兴趣区域的电阻确定半导体器件的多个轻掺杂漏极区域中的一个的宽度。 该方法还包括从半导体器件的多个轻掺杂漏区之一的宽度确定半导体器件的间隔物的宽度。