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1. 发明申请

US20120080725A1 VERTICAL TRANSISTOR MEMORY ARRAY 审中-公开
标题翻译：垂直晶体管存储阵列
公开(公告)号：US20120080725A1
公开(公告)日：2012-04-05
申请号：US12894405
申请日：2010-09-30
申请人： Peter Nicholas Manos , Young Pil Kim , Hyung-Kyu Lee , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir , Brian Lee , Dadi Setiadi
发明人： Peter Nicholas Manos , Young Pil Kim , Hyung-Kyu Lee , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir , Brian Lee , Dadi Setiadi
IPC分类号： H01L27/08 , H01L21/02
CPC分类号： H01L27/101 , G11C11/16 , H01L21/823487 , H01L27/228 , H01L27/2454 , H01L2924/0002 , H01L2924/00
摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.
摘要翻译：一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。导电互连元件沉积在至少选定的垂直柱晶体管上，并且非挥发性可变电阻存储单元沉积在导电互连层上以形成垂直晶体管存储器阵列。

2. 发明申请

US20110007588A1 Defective Bit Scheme for Multi-Layer Integrated Memory Device 有权
标题翻译：多层集成存储器件缺陷位方案
公开(公告)号：US20110007588A1
公开(公告)日：2011-01-13
申请号：US12502194
申请日：2009-07-13
申请人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
发明人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
IPC分类号： G11C29/00 , G11C29/04 , G11C15/00
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C29/44 , G11C29/808 , G11C2029/0403
摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
摘要翻译：本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

3. 发明授权

US07936622B2 Defective bit scheme for multi-layer integrated memory device 有权
标题翻译：多层集成存储器件的不良位方案
公开(公告)号：US07936622B2
公开(公告)日：2011-05-03
申请号：US12502194
申请日：2009-07-13
申请人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
发明人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
IPC分类号： G11C29/00
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C29/44 , G11C29/808 , G11C2029/0403
摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
摘要翻译：本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

4. 发明申请

US20100302849A1 NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE 有权
标题翻译：具有集成位线电容的NAND闪存
公开(公告)号：US20100302849A1
公开(公告)日：2010-12-02
申请号：US12474463
申请日：2009-05-29
申请人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
发明人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C11/005 , G11C16/26 , G11C2216/14
摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
摘要翻译：用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。在一些实施例中，易失性存储器单元是来自所述单元的行的动态随机存取存储器（DRAM）单元，其中每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元包括以NAND配置连接的闪存单元。

5. 发明申请

US20100037020A1 PIPELINED MEMORY ACCESS METHOD AND ARCHITECTURE THEREFORE 审中-公开
标题翻译：管道存储器访问方法和架构
公开(公告)号：US20100037020A1
公开(公告)日：2010-02-11
申请号：US12200118
申请日：2008-08-28
申请人： Hai Li , Yiran Chen , Hongyue Liu , Dadi Setiadi , Brian Lee
发明人： Hai Li , Yiran Chen , Hongyue Liu , Dadi Setiadi , Brian Lee
IPC分类号： G06F12/00
CPC分类号： G11C7/1039 , G11C8/10 , G11C8/18
摘要： A memory array and a method for accessing a memory array including: receiving an address from a host related to relevant data; accessing a first module based on the address received from the host, wherein accessing the first module includes: decoding the address for the first module; enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module; and outputting information regarding the first module; and accessing a second module based on the address received from the host, wherein accessing the second module includes: decoding the address for the second module; enabling a wordline based on the decoded address for the second module and sensing the contents of one or more bits at the decoded address for the second module; and outputting information regarding the second module, wherein the step of decoding the address for the second module occurs while the step of enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module occurs.
摘要翻译：一种用于访问存储器阵列的存储器阵列和方法，包括：从相关数据相关的主机接收地址; 基于从所述主机接收的地址访问第一模块，其中访问所述第一模块包括：解码所述第一模块的地址; 基于第一模块的解码地址启用字线，并感测第一模块的解码地址处的一个或多个位的内容; 并输出关于第一模块的信息; 以及基于从所述主机接收的地址访问第二模块，其中访问所述第二模块包括：对所述第二模块的地址进行解码; 基于第二模块的解码地址启用字线，并感测第二模块的解码地址处的一个或多个位的内容; 以及输出关于第二模块的信息，其中对第二模块的地址进行解码的步骤在基于第一模块的解码地址启用字线的步骤并且感测解码地址处的一个或多个位的内容的步骤第一个模块发生。

6. 发明授权

US08050092B2 NAND flash memory with integrated bit line capacitance 有权
标题翻译：具有集成位线电容的NAND闪存
公开(公告)号：US08050092B2
公开(公告)日：2011-11-01
申请号：US12474463
申请日：2009-05-29
申请人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
发明人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
IPC分类号： G11C11/34 , G11C11/24
CPC分类号： G11C11/005 , G11C16/26 , G11C2216/14
摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of the cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
摘要翻译：用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。在一些实施例中，易失性存储器单元是来自单元行的动态随机存取存储器（DRAM）单元，每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元包括以NAND配置连接的闪存单元。

7. 发明授权

US08541247B2 Non-volatile memory cell with lateral pinning 失效
标题翻译：具有侧向锁定的非易失性存储单元
公开(公告)号：US08541247B2
公开(公告)日：2013-09-24
申请号：US12973536
申请日：2010-12-20
申请人： Haiwen Xi , Antoine Khoueir , Brian Lee , Patrick J. Ryan
发明人： Haiwen Xi , Antoine Khoueir , Brian Lee , Patrick J. Ryan
IPC分类号： H01L27/115
CPC分类号： H01L43/08 , B82Y40/00 , G11C11/161 , G11C11/1675 , H01F10/3254 , H01F10/3272 , H01F10/329 , H01F41/303 , H01L43/12
摘要： An apparatus and associated method for a non-volatile memory cell, such as an STRAM cell. In accordance with various embodiments, a magnetic free layer is laterally separated from an antiferromagnetic layer (AFM) by a non-magnetic spacer layer and medially separated from a synthetic antiferromagnetic layer (SAF) by a magnetic tunneling junction. The AFM pins the magnetization of the SAF through contact with a pinning region of the SAF that laterally extends beyond the magnetic tunneling junction.
摘要翻译：用于非易失性存储器单元（例如STRAM单元）的装置和相关方法。根据各种实施例，无磁性层通过非磁性间隔层与反铁磁层（AFM）横向分离，并通过磁性隧道结从中间分离的合成反铁磁层（SAF）。 AFM通过与SAF的钉扎区域的接触来引导SAF的磁化，该区域横向延伸超过磁性隧道结。

8. 发明授权

US07939188B2 Magnetic stack design 有权
标题翻译：磁栈设计
公开(公告)号：US07939188B2
公开(公告)日：2011-05-10
申请号：US12501632
申请日：2009-07-13
申请人： Haiwen Xi , Antoine Khoueir , Brian Lee , Pat Ryan , Michael Tang , Insik Jin , Paul E. Anderson
发明人： Haiwen Xi , Antoine Khoueir , Brian Lee , Pat Ryan , Michael Tang , Insik Jin , Paul E. Anderson
IPC分类号： G11B5/39 , H01F10/08 , H01L43/08 , H01L43/12
CPC分类号： G01R33/098 , B82Y25/00 , G01R33/093 , G11C11/161 , H01F10/3254 , H01F10/3272 , H01F10/3286 , H01L43/08 , Y10T428/1114 , Y10T428/1143
摘要： A magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween. The stack includes an annular antiferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer. In some embodiments, the reference layer is larger than the free layer.
摘要翻译：具有具有可切换磁化取向的自由层的磁性堆叠，具有钉扎磁化取向的参考层和它们之间的阻挡层。堆叠包括与自由层电隔离并与参考层物理接触的环形反铁磁钉扎层。在一些实施例中，参考层大于自由层。

9. 发明授权

US08197953B2 Magnetic stack design 有权
标题翻译：磁栈设计
公开(公告)号：US08197953B2
公开(公告)日：2012-06-12
申请号：US13083693
申请日：2011-04-11
申请人： Haiwen Xi , Antoine Khoueir , Brian Lee , Pat Ryan , Michael Tang , Insik Jin , Paul E. Anderson
发明人： Haiwen Xi , Antoine Khoueir , Brian Lee , Pat Ryan , Michael Tang , Insik Jin , Paul E. Anderson
IPC分类号： G11B5/39 , H01F10/08 , H01L43/08 , H01L43/12
CPC分类号： G01R33/098 , B82Y25/00 , G01R33/093 , G11C11/161 , H01F10/3254 , H01F10/3272 , H01F10/3286 , H01L43/08 , Y10T428/1114 , Y10T428/1143
摘要： A magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween. The stack includes an annular antiferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer. In some embodiments, the reference layer is larger than the free layer.
摘要翻译：具有具有可切换磁化取向的自由层的磁性堆叠，具有钉扎磁化取向的参考层和它们之间的阻挡层。堆叠包括与自由层电隔离并与参考层物理接触的环形反铁磁钉扎层。在一些实施例中，参考层大于自由层。

10. 发明授权

US08487390B2 Memory cell with stress-induced anisotropy 有权
标题翻译：具有应力诱导各向异性的记忆体
公开(公告)号：US08487390B2
公开(公告)日：2013-07-16
申请号：US12418911
申请日：2009-04-06
申请人： Dimitar V. Dimitrov , Ivan Petrov Ivanov , Shuiyuan Huang , Antoine Khoueir , Brian Lee , John Daniel Stricklin , Olle Gunnar Heinonen , Insik Jin
发明人： Dimitar V. Dimitrov , Ivan Petrov Ivanov , Shuiyuan Huang , Antoine Khoueir , Brian Lee , John Daniel Stricklin , Olle Gunnar Heinonen , Insik Jin
IPC分类号： H01L29/82 , G11C11/14
CPC分类号： G11C11/1675 , G11C11/161
摘要： A magnetic memory element that has a stress-induced magnetic anisotropy. The memory element has a ferromagnetic free layer having a switchable magnetization orientation switchable, a ferromagnetic reference layer having a pinned magnetization orientation, and a non-magnetic spacer layer therebetween. The free layer may be circular, essentially circular or nearly circular.
摘要翻译：具有应力诱导的磁各向异性的磁记忆元件。存储元件具有可切换的磁化方向可转换的铁磁自由层，具有钉扎磁化取向的铁磁参考层和它们之间的非磁性间隔层。自由层可以是圆形的，基本上是圆形的或近似圆形的。

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